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2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-22dev-arm: Provide a GICv3 ITS ImplementationGiacomo Travaglini
This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
This code will be preserved through version control, but otherwise creates clutter and will rot in place since it's never compiled. Change-Id: Id265f6deac445116843956ea5cf1210d8127274e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-03dev: StreamID generation in DMA deviceGiacomo Travaglini
This patch is adding a StreamID tag to any DMA Packet. StreamIDs are tags which are used by IOMMUs to distinguish between different devices/functions. For PCI devices for example, the RID (Pci Bus number, Pci Device number, Pci Function number) could be stored in the Packet streamID field. For the DmaDevice base class, a simple pair of (Sub)StreamIDs has been provided. This is basically attaching a fixed (decided at python config time) streamID per device. If a derived device wants to implement a more elaborate packet tagger (for example if it wants to have more than one streamID), it needs to pass a different StreamID and SubstreamID to the DmaPort interface (like dmaAction). Change-Id: Ia17cf00437f7d3eb79211c1374134b174f90de59 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16749 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Store a PhysProxy port in Gicv3RedistGiacomo Travaglini
This spares us from retrieving the TC pointer every time we want to write/read to memory (LPIs) Change-Id: Iad76b5e69188fa0ac5c6777a3b2664b0fc66b12f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18600 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Add named variable for GICD_TYPER.IDBitsGiacomo Travaglini
This could be used by other GICv3 components to query the maximum number of implemented interrupt identifiers Change-Id: I132e50de331aea22523260bcefba7e961b53eccd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18599 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Read correct version of ICC_BPR registerGiacomo Travaglini
Some methods like groupPriorityMask check for the value of binary point registers. Those registers have a minimum value. Writing to those register is taking this into account, but the problem with the minimum value arises when the value is checked before sw is writing to them. In this case the minimum value won't be considered if the read is directly forwarded to the ISA class. Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18598 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Get a Gicv3Redistributor ptr from phys addressGiacomo Travaglini
The patch is adding the following method to Gicv3: * Gicv3::getRedistributorByAddr This will be needed by the ITS when trying to select the target redistributor after decoding the collection table entry (RDBase). Change-Id: I40e2c155f2fdc8ca6d3c20ff7a27702e02499f20 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18597 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Add several LPI methods in Gicv3RedistributorGiacomo Travaglini
Refactoring the existing in code in smaller methods will be crucial when adding the ITS module, which is a client for the redistributor class and which will require it to take different actions depending on the command it receives from software. List of methods: * read/writeEntryLPI Reading/Writing a byte from the LPI pending table * isPendingLPI Checks if the pINTID LPI is set. Knowing if an LPI is set is needed by the MOVI command, which is transfering the pending state from one redistributor to the other only if the LPI is pending. Change-Id: If14b1c28ff7f2aa20b12dcd822bf6a490cbe0270 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18596 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Take LPIs into account when interacting with CPUIF regsGiacomo Travaglini
Previous code was not handling LPIs when it came to activation/deactivation of interrupts. Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18595 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Fix GICv3 LPIs priority valueGiacomo Travaglini
Priority bits in the LPI configuration table entry are only the MSBits ([7:2]) and need to be shifted in order to get the real LPI priority value. Change-Id: Id04dd4fa9113a32712c73a7094df498de3c0d2b5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18594 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Disable LPI Configuration Table cachingGiacomo Travaglini
This is done since caching is not done correctly, and we don't care for now about performance degradations since the redistributor is using PhysProxy ports. Caching will make sense once the magical accesses will be replaced by real atomic/timing transactions. Change-Id: Iafe2a7843210111efc82c265bd0d5ec3cd9abb5a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18593 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Check EnableLPIs before checking for pending LPIsGiacomo Travaglini
Before reading the tables, GICR_PENDBASER and GICR_PROPBASER need to be properly set, and those will have a consistent value only once sw enables LPIs. Change-Id: Ifb87944a491045e7a13ce7a280c555cb0c1e47f4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: GICv3 LPI tables are using physical addressesGiacomo Travaglini
Change-Id: I439112f318720ae74c43a374fd3a524c607b3a23 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18591 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Fix GICv3 LPI loopGiacomo Travaglini
Loop was mistakenly increasing the upper bound of the iteration rather than the index variable itself. Change-Id: I0a5a7bc189bc0954a8a6d9581032c2ed902030da Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18590 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Fix Bitwise operation in GICv3Giacomo Travaglini
GICv3 LPI code is wrongly using the xor operator (^) in order to evaluate powers of two. Change-Id: Ib1131fd5940d334967a3741f8fd15d86625be356 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18589 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
Those types aren't generic or used outside of SPARC. Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18469 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28mem: Minimize the use of MemObject.Gabe Black
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-25dev-arm: Move GICv3 (Re)Ditributor address in Realview.pyGiacomo Travaglini
Base addresses for GICv3's Distributor and Redistributors are implementation defined: they depend on the platform rather than the model. This patch is then moving dist_addr and redist_addr initialization in Realview.py Change-Id: I1246df500262f4d3d5a38e62d0240945f90941ee Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18393 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
This is needed since there is a problem in the memory layout of VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping regions when reserving space for 256 PEs. GICv3 redistributors: 0x2c010000 - 0x30010000 PCI regions: 0x30000000 - 0x40000000 We fix this by cutting down the number of supported PEs to 128 Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Add GICv4 extension switch in GICv3Giacomo Travaglini
This is currently used only for determining which is the correct size of redistributors in memory (256KB in GICv4 and 128KB in GICv3) Change-Id: I2c07005e97167fde03548313c9927176788f31dd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18391 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Check for maximum number of supported PE in GICv3Giacomo Travaglini
This is currently set to 256 Change-Id: If7bb2847c22f29bfa0cb4ebf4a7984ee43ab4e29 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18390 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-24dev: Use the new Port role mechanism to make an EtherInt Port type.Gabe Black
This type always uses the same "ETHERNET" role, and all connections are symmetric and self compatible. Change-Id: I1d060f8c098d52ae9f65c052f816bc813590ff9c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18171 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Rename GIC maintenance interrupt from ppint to maint_intGiacomo Travaglini
ppint is a generic name which only reflects Arm recommendation of assigning the maintanance interrupt to a PPI (numbered 25) Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Fix GICv3 overflow for INTID > 256Giacomo Travaglini
SPIs can get to a maximum number of 1023, so that an uint8_t is not capable of representing all of them. Change-Id: I7a2c43b41ac93eabdfcf8311681240416b954177 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)Giacomo Travaglini
For SGIs and PPIs: * When ARE is 1 (only value supported in gem5) for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26dev-arm: Set/Unset dma coherent mode from pythonGiacomo Travaglini
With this patch it will be possible to automatically enable/disable the dma-coherent property for the GenericArmPciHost autogenerated DTB. This has been done by adding the _dma_coherent param. Change-Id: I1759fced74e42410462637ca77997a351314a90a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-23misc: missing override specifierAndrea Mondelli
Missing specifier of overridden virtual function declared in sim_object.hh Removed redundant "virtual" keyword Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
These are now pure virtual methods which more specialized port subclasses will need to implement. The SlavePort class implements them by ignoring them and then providing parallel functions for the MasterPort to call. The MasterPort's methods do basically what they did before, except now bind() uses dynamic cast to check if its peer is of the appropriate type and also to convert it into that type before connecting to it. Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15dev: Make EtherInt inherit from Port.Gabe Black
This way a common function can return EtherInt (and master and slave ports). Change-Id: I1215baaad918ef0352b228877241b2b6dd2503fc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17035 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-15dev: Make the EtherDevice class inherit EtherObject.Gabe Black
This avoids having to define two parallel versions of the getEthPort function, and the complex dynamic_cast macrame in connectPorts(). Change-Id: I24c09864005ff39a049e50d7245ff17e9480edea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17029 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15dev: Turn EtherObject into an interface class.Gabe Black
This class used to drive from SimObject so that it could be derived from to get both the interface and SimObject while still using single inheritance. With this change, EtherObject is now just an interface class with only one pure virtual function which can be inherited alongside SimObject. This makes it more flexible so that it can be used in places where you might want a different inheritance hierarchy, for instance to inherit from MemObject. Change-Id: I0f07664d104eed012cf4ce6e30c416ada19505a7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17028 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-14dev-arm: cleanup of gicv3 CPU interface code and fixesJairo Balart
Change-Id: I4643140f60da4dc9179b5bfed1e3ddd7c2f23091 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16484 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-12dev-arm: cleanup of gicv3 codeJairo Balart
Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-01dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
Reading ICV_PMR_EL1 should return the value the VMCR_EL2.VPMR bits which are aliased to the register. Change-Id: Id3e6dfb196f3726edaa3eddb244765598ed62334 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16545 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-01dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
Reading ICV_IGRPEN<n>_EL1 should return the value of VMCR_EL2.VENG0 and VMCR_EL2.VENG1 bits. Change-Id: Ia5d748cf60ba074cccf4c127ac479c5cb881773d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16544 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18dev-arm: LPI support for GICv3. This doesn't include an ITS model.Jairo Balart
Change-Id: Ia2c02cca4f95672d6361fba16201a56e2047ddb7 Reviewed-on: https://gem5-review.googlesource.com/c/16142 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
Physical memory ranges are now saved in Realview objects as pairs of addresses (start address and size). This patch is substituting them with a single AddrRange object. Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16206 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-01dev, arm: Removed contextId variableAnouk Van Laer
The contextId variable is only used by the debug flag and will prevent a more optimised binary (i.e. fast) from compiling. Change-Id: I6cefb5bc06d0d4b415df62f1278db53ba309fb87 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16042 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-24dev-arm: fix --generate-dtb for ARMCiro Santilli
Was failing with: NameError: global name 'FdtNode' is not defined The problem was introduced at: 75831ce5b7880b67c1aa2e0871ce16d5c01cadc7 Change-Id: I7e2ce0e5311e7814229945b9f4e7318a8652dc1f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15875 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
Other dev code was already switched over. This code was written before the switch over (or unaware of it), and checked in after. Change-Id: Ibb9e9e4300d01cc46e4dae668274debc2a4989ba Reviewed-on: https://gem5-review.googlesource.com/c/15755 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are some remaining types, specifically the vector registers and the CCReg. I'm less familiar with these new types of registers, and so will look at getting rid of them at some later time. Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b Reviewed-on: https://gem5-review.googlesource.com/c/13624 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7 Reviewed-on: https://gem5-review.googlesource.com/c/14255 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1 Reviewed-on: https://gem5-review.googlesource.com/c/13436 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-04dev, arm: Warn on PL011 DMA disableJan-Peter Larsson
The PL011 spec specifies a DMACR register at offset 0x48, which isn't implemented in the model. Currently any attempt to access the register results in a panic. This change swaps the panic for a warning only when software writes into DMACR to disable DMA, keeping the panic otherwise. Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15279 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Added VGIC GICV_IIDR responseAnouk Van Laer
Change-Id: I60e8eadbbbf07c0f8b726213fd580aeb0dd0e00b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15278 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Implement GIC-400 model from GicV2Giacomo Travaglini
Implementation registers for the GICv2 model currently hold values referring to a GIC-400 implementation. This patch is making them parametrizable so that it is possible to instantiate a GIC-400 model. The patch is also modifying Realview platform to use new GIC-400 model in lieau of GICv2. Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15277 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-22 12:54:59 +0000