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AgeCommit message (Expand)Author
2019-09-05dev-arm: Implement invalidateASID in SMMUv3 WalkCacheJan-Peter Larsson
2019-09-05dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCacheAdrian Herrera
2019-09-04dev: Templatize PioPort.Gabe Black
2019-08-27cpu, dev, mem: Use the new Port methods.Gabe Black
2019-08-26dev-arm: Fix GICv3 ITS indexing errorGiacomo Travaglini
2019-08-26dev-arm: Fix GITS_BASER initialization/accessGiacomo Travaglini
2019-08-22dev-arm: Start using GITS_CTLR.quiescent bitGiacomo Travaglini
2019-08-22dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)Giacomo Travaglini
2019-08-22dev-arm,system-arm: missing GICv3 ranges propertyAdrian Herrera
2019-08-20dev-arm: Add redistributor-stride property to GICv3Giacomo Travaglini
2019-08-20dev-arm: Add GITS_PIDR2 register to the ITS memory mapGiacomo Travaglini
2019-08-20dev-arm: Add Gicv3Distributor members for GICv3 GICD_PIDRxGiacomo Travaglini
2019-08-12dev-arm: Enable DTB autogeneration in GICv3Giacomo Travaglini
2019-08-12dev-arm: Fix PCI node's interrupt-map propertyGiacomo Travaglini
2019-08-12dev-arm: Use FdtState to generate GIC properitesGiacomo Travaglini
2019-08-07dev-arm: Perform SMMUv3 CFG Invalidation at device interfaceGiacomo Travaglini
2019-07-30dev-arm: Rewrite SMMUv3 CommandsGiacomo Travaglini
2019-07-25dev-arm: Fix SMMUv3 CMDQ wrappingGiacomo Travaglini
2019-07-25dev-arm: Polish SMMUv3 CMDQ setupGiacomo Travaglini
2019-07-25dev-arm: Define enum masks for SMMU_CR0 registerGiacomo Travaglini
2019-07-25dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCacheGiacomo Travaglini
2019-07-25dev-arm: SMMUv3 Table walks using TnSZGiacomo Travaglini
2019-07-25dev-arm: Use override keyword for SMMUv3 PTOPSGiacomo Travaglini
2019-07-25dev-arm: Add 16K granule support to SMMUv3 modelMichiel Van Tol
2019-07-19dev-arm: clang compatibility fix, added missing overridesMatteo Andreozzi
2019-07-16dev-arm: Fix SMMUv3 ContextDescriptor pointer shiftGiacomo Travaglini
2019-07-10dev-arm: A9SCU fixupTiago Muck
2019-07-01dev-arm: Use global import path for MemObjectGiacomo Travaglini
2019-06-26dev-arm: Remove un-needed Q_CONS_PROD_MASK macroGiacomo Travaglini
2019-06-26dev-arm: drain implementation for SMMUv3Adrian Herrera
2019-06-26dev-arm: pending SMMU transl update on constructor/destructorAdrian Herrera
2019-06-17dev-arm: Reapply GICv3 changes that were lost during refactoringGiacomo Travaglini
2019-06-06dev-arm: Implement a SMMUv3 modelStanislaw Czerniawski
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-22dev-arm: Provide a GICv3 ITS ImplementationGiacomo Travaglini
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
2019-05-03dev: StreamID generation in DMA deviceGiacomo Travaglini
2019-05-02dev-arm: Store a PhysProxy port in Gicv3RedistGiacomo Travaglini
2019-05-02dev-arm: Add named variable for GICD_TYPER.IDBitsGiacomo Travaglini
2019-05-02dev-arm: Read correct version of ICC_BPR registerGiacomo Travaglini
2019-05-02dev-arm: Get a Gicv3Redistributor ptr from phys addressGiacomo Travaglini
2019-05-02dev-arm: Add several LPI methods in Gicv3RedistributorGiacomo Travaglini
2019-05-02dev-arm: Take LPIs into account when interacting with CPUIF regsGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPIs priority valueGiacomo Travaglini
2019-05-02dev-arm: Disable LPI Configuration Table cachingGiacomo Travaglini
2019-05-02dev-arm: Check EnableLPIs before checking for pending LPIsGiacomo Travaglini
2019-05-02dev-arm: GICv3 LPI tables are using physical addressesGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPI loopGiacomo Travaglini
2019-05-02dev-arm: Fix Bitwise operation in GICv3Giacomo Travaglini
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
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