gem5 - gem5

Age	Commit message (Collapse)	Author
2018-10-17	gpu-compute: Explicitly use little endian packet accessors.	Gabe Black
	The gpu ISA doesn't have a well defined endianness, but it really should. It seems that the GPU is only used with x86, and in that context it would be little endian. Change-Id: I1620906564a77f44553fbf6d788866e017b6054b Reviewed-on: https://gem5-review.googlesource.com/c/13463 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-16	style: fix amd license and style issues	Tony Gutierrez
	Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5 Reviewed-on: https://gem5-review.googlesource.com/10463 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-27	sim,cpu,mem,arch: Introduced MasterInfo data structure	Giacomo Travaglini
	With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-07-12	gpu-compute: Refactor some Event subclasses to lambdas	Sean Wilson
	Change-Id: Ic1332b8e8ba0afacbe591c80f4d06afbf5f04bd9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3922 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2016-09-16	gpu-compute: fix typo in GPUDispatcher	Tony Gutierrez

2016-09-16	gpu-compute: Adding ioctl for HW context size	Alexandru Dutu
	Adding runtime support for determining the memory required by a SIMD engine when executing a particular wavefront.
2016-09-16	gpu-compute: Wavefront refactoring	Alexandru Dutu
	Renaming members of the Wavefront class in accordance with the style guide.
2016-06-09	gpu-compute: parametrize Wavefront size	jkalamat
	Eliminate the VSZ constant that defined the Wavefront size (in numbers of work items); replaced it with a parameter in the GPU.py configuration script. Changed all data structures dependent on the Wavefront size to be dynamically sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at initialization time.
2016-04-07	mem: Remove threadId from memory request class	Mitch Hayenga
	In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
2016-01-19	gpu-compute: AMD's baseline GPU model	Tony Gutierrez