summaryrefslogtreecommitdiff
path: root/src/gpu-compute
AgeCommit message (Collapse)Author
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
Every usage of Request* in the code has been replaced with the RequestPtr alias. This is a preparing patch for when RequestPtr will be the typdefed to a smart pointer to Request rather then a raw pointer to Request. Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10995 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-30gpu-compute: use X86ISA::TlbEntry over GpuTlbEntryBrandon Potter
GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It wrapped the class and included an extra member "valid". This member was intended to report on the validity of the entry, however it introduced bugs when folks forgot to set field properly in the code. So, instead of keeping the extra field which we might forget to set, we track validity by using nullptr for invalid tlb entries (as the tlb entries are dynamically allocated). This saves on the extra class definition and prevents bugs creeping into the code since the checks are intrinsically tied into accessing any of the X86ISA::TlbEntry members. This changeset fixes the issues introduced by a8d030522, a4e722725, and 2a15bfd79. Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2 Reviewed-on: https://gem5-review.googlesource.com/10481 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-16style: fix amd license and style issuesTony Gutierrez
Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5 Reviewed-on: https://gem5-review.googlesource.com/10463 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-15gpu-compute: Cleanup the scheduler a bitTony Gutierrez
Change-Id: If2c626544f208e15c91be975dee9253126862ced Reviewed-on: https://gem5-review.googlesource.com/10222 Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-17gpu-compute: fix bad asserts in gpu tlb and cu tlb portTony Gutierrez
change 2a15bfd79ced20a6d4cbf0a0a4c2fbb1444b9a44 introduced a few bugs in the tlb of the cu. asserts in the gpu tlb and cu expected the page table lookup() function to return a bool, and this value was used directly in the gpu tlb's assert and it was kept in the gpu tlb entry, where later the cu would assert that it is true. this change fixes the issue by checking the validity of the pte pointer returned by lookup() in order to set the validity of the tlb entry itself. Change-Id: Ief1f205db65f1911fd132acd314e4407c5e3ffdf Reviewed-on: https://gem5-review.googlesource.com/10001 Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-03-22hsail: Get rid of an inert private member of StorageSpace.Gabe Black
The "segment" private element in this class was only ever set to zero on construction, and then used to index into a list of segment names to get the string "none" in a DPRINTF. If debugging was turned off, there would be no consumers of that variable, and that upset g++. This change removes the essentially useless variable, and also that bit of text in the DPRINTF. Change-Id: I3f85db4af5f0678768243daf84b8d698350af931 Reviewed-on: https://gem5-review.googlesource.com/9221 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-01-23tarch, mem: Abstract the data stored in the SE page tables.Gabe Black
Rather than store the actual TLB entry that corresponds to a mapping, we can just store some abstracted information (address, a few flags) and then let the caller turn that into the appropriate entry. There could potentially be some small amount of overhead from creating entries vs. storing them and just installing them, but it's likely pretty minimal since that only happens on a TLB miss (ideally rare), and, if it is problematic, there could be some preallocated TLB entries which are just minimally filled in as necessary. This has the nice effect of finally making the page tables ISA agnostic. Change-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317 Reviewed-on: https://gem5-review.googlesource.com/7350 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-20arch, mem: Make the page table lookup function return a pointer.Gabe Black
This avoids having a copy in the lookup function itself, and the declaration of a lot of temporary TLB entry pointers in callers. The gpu TLB seems to have had the most dependence on the original signature of the lookup function, partially because it was relying on a somewhat unsafe copy to a TLB entry using a base class pointer type. Change-Id: I8b1cf494468163deee000002d243541657faf57f Reviewed-on: https://gem5-review.googlesource.com/7343 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.). Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-07-12gpu-compute: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: Ic1332b8e8ba0afacbe591c80f4d06afbf5f04bd9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3922 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-06-20cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapperSean Wilson
Change-Id: Idd5992463bcf9154f823b82461070d1f1842cea3 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3746 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Move memState into its own fileBrandon Potter
The Process class is full of implementation details and structures related to SE Mode. This changeset factors out an internal class from Process and moves it into a separate file. The purpose behind doing this is to clean up the code and make it a bit more modular. Change-Id: Ic6941a1657751e8d51d5b6b1dcc04f1195884280 Reviewed-on: https://gem5-review.googlesource.com/2263 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-07gpu-compute: Fix Python/C++ object hierarchy discrepanciesAndreas Sandberg
The GPUCoalescer and the Shader classes have different base classes in C++ and Python. This causes subtle bugs in SWIG and compilation errors for PyBind. Change-Id: I1ddd2a8ea43f083470538ddfea891347b21d14d8 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2228 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
2017-02-27syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess ↵Brandon Potter
simulations Modifies the clone system call and adds execve system call. Requires allowing processes to steal thread contexts from other processes in the same system object and the ability to detach pieces of process state (such as MemState) to allow dynamic sharing.
2017-02-27gpu-compute: remove unnecessary member from classTony Gutierrez
The clang compiler complains that the wavefront member in the GpuISA class is unused. This changeset removes the member, because it does not appear serve a purpose.
2017-02-27gpu-compute: mark functions with override if replacing virtualBrandon Potter
The clang compiler is more stringent than the recent versions of GCC when dealing with overrides. This changeset adds the specifier to the methods which need it to silence the compiler.
2016-11-09syscall_emul: [patch 10/22] refactor fdentry and add fdarray classBrandon Potter
Several large changes happen in this patch. The FDEntry class is rewritten so that file descriptors now correspond to types: 'File' which is normal file-backed file with the file open on the host machine, 'Pipe' which is a pipe that has been opened on the host machine, and 'Device' which does not have an open file on the host yet acts as a pseudo device with which to issue ioctls. Other types which might be added in the future are directory entries and sockets (off the top of my head). The FDArray class was create to hold most of the file descriptor handling that was stuffed into the Process class. It uses shared pointers and the std::array type to hold the FDEntries mentioned above. The changes to these two classes needed to be propagated out to the rest of the code so there were quite a few changes for that. Also, comments were added where I thought they were needed to help others and extend our DOxygen coverage.
2016-11-09syscall_emul: [patch 5/22] remove LiveProcess class and use Process insteadBrandon Potter
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process.
2016-11-09style: [patch 3/22] reduce include dependencies in some headersBrandon Potter
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include.
2016-12-02hsail: remove the panic guarding function directivesBrandon Potter
HSA functions calls are still not supported properly with HSAIL, but the recent AMP runtime modifications rely on being able to parse the BRIG/HSAIL files that are extracted from the application binaries. We need to parse the function call HSAIL definitions, but we do not actually need to make the function calls. The reason that this happens is that HCC appends a set of routines to every HSAIL binary that it creates. These extra, unnecessary routines exist in the HCC source as a file; this file is cat'd onto everything that the compiler outputs before being assembled into the application's binary. HCC does this because it might call these helper functions. However, it doesn't actually appear to do so in the AMP codes so we just parse these functions with the HSAIL parser and then ignore them.
2016-11-21gpu-compute: fix segfault when constructing GPUExecContextTony Gutierrez
the GPUExecContext context currently stores a reference to its parent WF's GPUISA object, however there are some special instructions that do not have an associated WF. when these objects are constructed they set their WF pointer to null, which causes the GPUExecContext to segfault when trying to dereference the WF pointer to get at the WF's GPUISA object. here we change the GPUISA reference in the GPUExecContext class to a pointer so that it may be set to null.
2016-11-21gpu-compute: init valid field of GpuTlbEntry in default ctorTony Gutierrez
valid field for GpuTlbEntry is not set in the default ctor, which can lead to strange behavior, and is also flagged by UBSAN.
2016-10-26hsail,gpu-compute: fixes to appease clang++Tony Gutierrez
fixes to appease clang++. tested on: Ubuntu clang version 3.5.0-4ubuntu2~trusty2 (tags/RELEASE_350/final) (based on LLVM 3.5.0) Ubuntu clang version 3.6.0-2ubuntu1~trusty1 (tags/RELEASE_360/final) (based on LLVM 3.6.0) the fixes address the following five issues: 1) the exec continuations in gpu_static_inst.hh were marked as protected when they should be public. here we mark them as public 2) the Abs instruction uses std::abs() in its execute method. because Abs is templated, it can also operate on U32 and U64, types, which cause Abs::execute() to pass uint32_t and uint64_t types to std::abs() respectively. this triggers a warning because std::abs() has no effect in this case. to rememdy this we add template specialization for the execute() method of Abs when its template paramter is U32 or U64. 3) Some potocols that utilize the code in cprintf.hh were missing includes to BoolVec.hh, which defines operator<< for the BoolVec type. This would cause issues when the generated code would try to pass a BoolVec type to a method in cprintf.hh that used operator<< on an instance of a BoolVec. 4) Surprise, clang doesn't like it when you clobber all the bits in a newly allocated object. I.e., this code: tlb = new GpuTlbEntry\[size\]; std::memset(tlb, 0, sizeof(GpuTlbEntry) \* size); Let's use std::vector to track the TLB entries in the GpuTlb now... 5) There were a few variables used only in DPRINTFs, so we mark them with M5_VAR_USED.
2016-10-26gpu-compute: support in-order data delivery in GM pipeTony Gutierrez
this patch adds an ordered response buffer to the GM pipeline to ensure in-order data delivery. the buffer is implemented as a stl ordered map, which sorts the request in program order by using their sequence ID. when requests return to the GM pipeline they are marked as done. only the oldest request may be serviced from the ordered buffer, and only if is marked as done. the FIFO response buffers are kept and used in OoO delivery mode
2016-10-26gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()Tony Gutierrez
for HSAIL an operand's indices into the register files may be calculated trivially, because the operands are always read from a register file, or are an immediate. for machine ISA, however, an op selector may specify special registers, or may specify special SGPRs with an alias op selector value. the location of some of the special registers values are dependent on the size of the RF in some cases. here we add a way for the underlying getRegisterIndex() method to know about the size of the RFs, so that it may find the relative positions of the special register values.
2016-10-26gpu-compute: use System cache line size in the GPUTony Gutierrez
2016-10-26gpu-compute, hsail: make the PC a byte address, not an instruction indexTony Gutierrez
currently the PC is incremented on an instruction granularity, and not as an instruction's byte address. machine ISA instructions assume the PC is a byte address, and is incremented accordingly. here we make the GPU model, and the HSAIL instructions treat the PC as a byte address as well.
2016-10-26gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WFTony Gutierrez
the GPUISA class is meant to encapsulate any ISA-specific behavior - special register accesses, isa-specific WF/kernel state, etc. - in a generic enough way so that it may be used in ISA-agnostic code. gpu-compute: use the GPUISA object to advance the PC the GPU model treats the PC as a pointer to individual instruction objects - which are store in a contiguous array - and not a byte address to be fetched from the real memory system. this is ok for HSAIL because all instructions are considered by the model to be the same size. in machine ISA, however, instructions may be 32b or 64b, and branches are calculated by advancing the PC by the number of words (4 byte chunks) it needs to advance in the real instruction stream. because of this there is a mismatch between the PC we use to index into the instruction array, and the actual byte address PC the ISA expects. here we move the PC advance calculation to the ISA so that differences in the instrucion sizes may be accounted for in generic way.
2016-10-26gpu-compute: add instruction mix stats for the gpuTony Gutierrez
2016-10-26gpu-compute, hsail: call discardFetch() from the WFTony Gutierrez
because every taken branch causes fetch to be discarded, we move the call to the WF to avoid to have to call it from each and every branch instruction type.
2016-10-26hsail, gpu-compute: remove doGm/SmReturn add completeAccTony Gutierrez
we are removing doGmReturn from the GM pipe, and adding completeAcc() implementations for the HSAIL mem ops. the behavior in doGmReturn is dependent on HSAIL and HSAIL mem ops, however the completion phase of memory ops in machine ISA can be very different, even amongst individual machine ISA mem ops. so we remove this functionality from the pipeline and allow it to be implemented by the individual instructions.
2016-10-26gpu-compute: remove inst enums and use bit flag for attributesTony Gutierrez
this patch removes the GPUStaticInst enums that were defined in GPU.py. instead, a simple set of attribute flags that can be set in the base instruction class are used. this will help unify the attributes of HSAIL and machine ISA instructions within the model itself. because the static instrution now carries the attributes, a GPUDynInst must carry a pointer to a valid GPUStaticInst so a new static kernel launch instruction is added, which carries the attributes needed to perform a the kernel launch.
2016-10-26gpu-compute: move disassemle() implementation to GPUStaticInstTony Gutierrez
2016-10-26gpu-compute, arch: add some methods to the base inst classes for ISA supportTony Gutierrez
2016-10-04gpu-compute: Added method to compute the actual workgroup sizeAlexandru Dutu
This patch adds a method to the Wavefront class to compute the actual workgroup size. This can be different from the maximum workgroup size specified when launching the kernel through the NDRange object. Current solution is still not optimal, as we are computing these for each wavefront and the dispatcher also needs to have this information and can't actually call Wavefront::computeActuallWgSz before the wavefronts are being created. A long term solution would be to have a Workgroup class that deals with all these details.
2016-09-16gpu-compute: fix typo in GPUDispatcherTony Gutierrez
2016-09-16gpu-compute: Adding context serialization methods to WavefrontAlexandru Dutu
This patch adds methods to serialize the context of a particular wavefront to the simulated system memory. Context serialization is used when a wavefront is preempeted (i.e. context switch).
2016-09-16gpu-compute: Refactoring Wavefront::dynWaveIdAlexandru Dutu
2016-09-16gpu-compute: Adding vector register file debug messagesAlexandru Dutu
This patch introduces DPRINTFs for reading and writing to and from the vector register file.
2016-09-16gpu-compute: Changing reconvergenceStack typeAlexandru Dutu
std::stack has no iterators, therefore the reconvergence stack can't be iterated without poping elements off. We will be using std::list instead to be able to iterate for saving and restoring purposes.
2016-09-16gpu-compute: Adding ioctl for HW context sizeAlexandru Dutu
Adding runtime support for determining the memory required by a SIMD engine when executing a particular wavefront.
2016-09-16gpu-compute: Wavefront refactoringAlexandru Dutu
Renaming members of the Wavefront class in accordance with the style guide.
2016-09-16gpu-compute: Remove WFContextAlexandru Dutu
WFContext struct is currently unused and it has been rendered not useful in saving and restoring the context of a Wavefront. Wavefront class should be sufficient for that purpose and the runtime can figure out the memory size it will need to allocate for a Wavefront through an IOCTL.
2016-09-13gpu-compute: Fix bug with return in cfgMichael LeBeane
Connecting basic blocks would stop too early in kernels where ret was not the last instruction. This patch allows basic blocks after the ret instruction to be properly connected.
2016-06-09gpu-compute: parametrize Wavefront sizejkalamat
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work items); replaced it with a parameter in the GPU.py configuration script. Changed all data structures dependent on the Wavefront size to be dynamically sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at initialization time.
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
Fixing an issue with regStats not calling the parent class method for most SimObjects in Gem5. This causes issues if one adds new stats in the base class (since they are never initialized properly!). Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-03gpu-compute: Fixed a bug in global memory pipelineTuan Ta
Added a condition when inflightStores is incremented to prevent a deadlock caused by many memory fence requests generated by a CU
2016-05-16gpu-compute: fix bug in GPUDynInst::isScalarRegister()Tony Gutierrez