| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-11-14 | mem: Clarify unit of DRAM controller buffer size | Andreas Hansson |
| 2014-10-20 | mem: Add DRAM device size and check against config | Omar Naji |
| 2014-07-25 | mem: Add missig timing and current parameters to DRAM configs | Omar Naji |
| 2014-10-09 | mem: Remove DRAMSim2 DDR3 configuration | Omar Naji |
| 2014-09-20 | mem: Add DDR4 bank group timing | Wendy Elsasser |
| 2014-09-20 | mem: Add memory rank-to-rank delay | Wendy Elsasser |
| 2014-05-09 | mem: Update DDR3 and DDR4 based on datasheets | Andreas Hansson |
| 2014-05-09 | mem: Add DRAM cycle time | Andreas Hansson |
| 2014-05-09 | mem: Add tRTP to the DRAM controller | Andreas Hansson |
| 2014-05-09 | mem: Add tWR to DRAM activate and precharge constraints | Andreas Hansson |
| 2014-05-09 | mem: Make DRAM read/write switching less conservative | Andreas Hansson |
| 2014-03-23 | mem: Rename SimpleDRAM to a more suitable DRAMCtrl | Andreas Hansson |
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