| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-05-09 | mem: Update DDR3 and DDR4 based on datasheets | Andreas Hansson |
| 2014-05-09 | mem: Add DRAM cycle time | Andreas Hansson |
| 2014-05-09 | mem: Add tRTP to the DRAM controller | Andreas Hansson |
| 2014-05-09 | mem: Add tWR to DRAM activate and precharge constraints | Andreas Hansson |
| 2014-05-09 | mem: Make DRAM read/write switching less conservative | Andreas Hansson |
| 2014-03-23 | mem: Rename SimpleDRAM to a more suitable DRAMCtrl | Andreas Hansson |
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |