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path: root/src/mem/DRAMCtrl.py
AgeCommit message (Expand)Author
2015-06-07mem: Add HMC Timing ParametersMatthias Jung
2015-02-03config: Adjust DRAM channel interleaving defaultsAndreas Hansson
2014-12-02mem: Add a GDDR5 DRAM configOmar Naji
2014-11-14mem: Clarify unit of DRAM controller buffer sizeAndreas Hansson
2014-10-20mem: Add DRAM device size and check against configOmar Naji
2014-07-25mem: Add missig timing and current parameters to DRAM configsOmar Naji
2014-10-09mem: Remove DRAMSim2 DDR3 configurationOmar Naji
2014-09-20mem: Add DDR4 bank group timingWendy Elsasser
2014-09-20mem: Add memory rank-to-rank delayWendy Elsasser
2014-05-09mem: Update DDR3 and DDR4 based on datasheetsAndreas Hansson
2014-05-09mem: Add DRAM cycle timeAndreas Hansson
2014-05-09mem: Add tRTP to the DRAM controllerAndreas Hansson
2014-05-09mem: Add tWR to DRAM activate and precharge constraintsAndreas Hansson
2014-05-09mem: Make DRAM read/write switching less conservativeAndreas Hansson
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson