gem5 - gem5

Age	Commit message (Expand)	Author
2019-10-29	mem: Fix DRAM controller to operate on its own address space	Nikos Nikoleris
2019-06-06	mem: Option to toggle DRAM low-power states	Matthew Poremba
2019-02-12	python: Don't assume SimObjects live in the global namespace	Andreas Sandberg
2018-09-07	mem: Make DRAMCtrl a QoS-aware Memory Controller	Matteo Andreozzi
2018-05-18	mem: Add support for more flexible DRAM timing and topologies	Wendy Elsasser
2018-02-09	Fix DDR4_2400_8x8 DRAMCTRL configuration	Wendy Elsasser
2017-02-14	mem: Update DRAM configuration names	Wendy Elsasser
2016-10-13	mem: add DRAM powerdown current	Omar Naji
2016-10-13	mem: update DDR3 die revision	Omar Naji
2016-10-13	mem: add DRAM powerdown timing	Omar Naji
2016-10-13	mem: make DDR4 x16	Omar Naji
2015-11-03	mem: hmc: minor fixes	Erfan Azarkhish
2015-09-22	mem: Add initial HBM configurations	Wendy Elsasser
2015-07-03	mem: Increase the default buffer sizes for the DDR4 controller	Andreas Hansson
2015-06-07	mem: Add HMC Timing Parameters	Matthias Jung
2015-02-03	config: Adjust DRAM channel interleaving defaults	Andreas Hansson
2014-12-02	mem: Add a GDDR5 DRAM config	Omar Naji
2014-11-14	mem: Clarify unit of DRAM controller buffer size	Andreas Hansson
2014-10-20	mem: Add DRAM device size and check against config	Omar Naji
2014-07-25	mem: Add missig timing and current parameters to DRAM configs	Omar Naji
2014-10-09	mem: Remove DRAMSim2 DDR3 configuration	Omar Naji
2014-09-20	mem: Add DDR4 bank group timing	Wendy Elsasser
2014-09-20	mem: Add memory rank-to-rank delay	Wendy Elsasser
2014-05-09	mem: Update DDR3 and DDR4 based on datasheets	Andreas Hansson
2014-05-09	mem: Add DRAM cycle time	Andreas Hansson
2014-05-09	mem: Add tRTP to the DRAM controller	Andreas Hansson
2014-05-09	mem: Add tWR to DRAM activate and precharge constraints	Andreas Hansson
2014-05-09	mem: Make DRAM read/write switching less conservative	Andreas Hansson
2014-03-23	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	Andreas Hansson