Age | Commit message (Expand) | Author |
2015-11-03 | mem: hmc: serial link model | Erfan Azarkhish |
2015-11-03 | mem: hmc: adds controller | Erfan Azarkhish |
2015-08-04 | mem: Move trace functionality from the CommMonitor to a probe | Andreas Sandberg |
2015-08-04 | mem: Redesign the stack distance calculator as a probe | Andreas Sandberg |
2014-12-23 | mem: Add a stack distance calculator | Kanishk Sugand |
2014-12-23 | mem: Add MemChecker and MemCheckerMonitor | Marco Elver |
2014-10-16 | mem: Add ExternalMaster and ExternalSlave ports | Andrew Bardsley |
2014-07-29 | mem: Add DRAMPower wrapping class | Omar Naji |
2014-09-20 | mem: Rename Bus to XBar to better reflect its behaviour | Andreas Hansson |
2014-09-20 | mem: Simple Snoop Filter | Stephan Diestelhorst |
2014-08-28 | mem: adding architectural page table support for SE mode | Alexandru |
2014-06-30 | mem: DRAMPower trace output | Andreas Hansson |
2014-05-09 | mem: Add DRAM power states to the controller | Andreas Hansson |
2014-03-23 | mem: Rename SimpleDRAM to a more suitable DRAMCtrl | Andreas Hansson |
2014-03-23 | ruby: Move Ruby debug flags to ruby dir and remove stale options | Andreas Hansson |
2014-03-23 | mem: Include the DRAMSim2 wrapper in NULL build | Andreas Hansson |
2014-02-18 | mem: Add a wrapped DRAMSim2 memory controller | Andreas Hansson |
2013-11-01 | mem: Use the same timing calculation for DRAM read and write | Ani Udipi |
2013-09-04 | arch: Resurrect the NOISA build target and rename it NULL | Andreas Hansson |
2013-01-07 | mem: Add tracing support in the communication monitor | Andreas Hansson |
2012-12-11 | ruby: add a prefetcher | Nilay Vaish |
2012-09-25 | mem: Add a gasket that allows memory ranges to be re-mapped. | Ali Saidi |
2012-09-21 | DRAM: Introduce SimpleDRAM to capture a high-level controller | Andreas Hansson |
2012-08-22 | Bridge: Remove NACKs in the bridge and unify with packet queue | Andreas Hansson |
2012-07-10 | ruby: banked cache array resource model | Brad Beckmann |
2012-07-10 | ruby: tag and data cache access support | Joel Hestness |
2012-05-31 | Bus: Split the bus into a non-coherent and coherent bus | Andreas Hansson |
2012-05-09 | MEM: Add the communication monitor | Andreas Hansson |
2012-04-06 | MEM: Enable multiple distributed generalized memories | Andreas Hansson |
2012-03-30 | MEM: Remove legacy DRAM in preparation for memory updates | Andreas Hansson |
2012-03-22 | MEM: Split SimpleTimingPort into PacketQueue and ports | Andreas Hansson |
2012-02-24 | MEM: Move all read/write blob functions from Port to PortProxy | Andreas Hansson |
2012-01-28 | Merge with the main repo. | Gabe Black |
2012-01-16 | Merge yet again with the main repository. | Gabe Black |
2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
2012-01-11 | Ruby Debug Flags: Remove one, add another | Nilay Vaish |
2012-01-11 | Ruby: Add infrastructure for recording cache contents | Nilay Vaish |
2012-01-07 | Merge with main repository. | Gabe Black |
2011-11-14 | Ruby: Process packet instead of RubyRequest in Sequencer | Nilay Vaish |
2011-10-16 | SE/FS: Turn on the page table class in FS. | Gabe Black |
2011-10-16 | SE/FS: Build in the tport in FS mode. | Gabe Black |
2011-10-16 | SE/FS: Build/expose vport in SE mode. | Gabe Black |
2011-06-02 | scons: rename TraceFlags to DebugFlags | Nathan Binkert |
2011-03-19 | RubyPort: minor fixes to trace flag and dprintfs | Brad Beckmann |
2011-01-10 | ruby: get rid of ruby's Debug.hh | Nathan Binkert |
2010-12-01 | ruby: Converted old ruby debug calls to M5 debug calls | Nilay Vaish |
2010-11-19 | SCons: Support building without an ISA | Ali Saidi |
2010-01-29 | ruby: Convert most Ruby objects to M5 SimObjects. | Steve Reinhardt |
2009-11-18 | ruby: Support for merging ALPHA_FS and ruby | Brad Beckmann |
2009-05-11 | ruby: add RUBY sticky option that must be set to add ruby to the build | Nathan Binkert |