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path: root/src/mem/SimpleDRAM.py
AgeCommit message (Expand)Author
2013-08-19config: Command line support for multi-channel memoryAndreas Hansson
2013-08-19mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAMAmin Farmahini
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-05-30mem: Add static latency to the DRAM controllerAndreas Hansson
2013-05-30mem: Add a LPDDR3-1600 configurationAndreas Hansson
2013-05-30mem: Adapt the LPDDR2 to match a single x32 channelAndreas Hansson
2013-04-22mem: Address mapping with fine-grained channel interleavingAndreas Hansson
2013-04-22mem: More descriptive enum names for address mappingAndreas Hansson
2013-04-22mem: Add a WideIO DRAM configurationAndreas Hansson
2013-03-01mem: Add a method to build multi-channel DRAM configurationsAndreas Hansson
2013-03-01mem: Add support for multi-channel DRAM configurationsAndreas Hansson
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-31mem: Add tTAW and tFAW to the SimpleDRAM modelAni Udipi
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-09-21DRAM: Introduce SimpleDRAM to capture a high-level controllerAndreas Hansson
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