| Age | Commit message (Expand) | Author |
|---|
| 2013-08-19 | config: Command line support for multi-channel memory | Andreas Hansson |
| 2013-08-19 | mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM | Amin Farmahini |
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2013-05-30 | mem: More descriptive DRAM config names | Andreas Hansson |
| 2013-05-30 | mem: Add static latency to the DRAM controller | Andreas Hansson |
| 2013-05-30 | mem: Add a LPDDR3-1600 configuration | Andreas Hansson |
| 2013-05-30 | mem: Adapt the LPDDR2 to match a single x32 channel | Andreas Hansson |
| 2013-04-22 | mem: Address mapping with fine-grained channel interleaving | Andreas Hansson |
| 2013-04-22 | mem: More descriptive enum names for address mapping | Andreas Hansson |
| 2013-04-22 | mem: Add a WideIO DRAM configuration | Andreas Hansson |
| 2013-03-01 | mem: Add a method to build multi-channel DRAM configurations | Andreas Hansson |
| 2013-03-01 | mem: Add support for multi-channel DRAM configurations | Andreas Hansson |
| 2013-01-31 | mem: Add DDR3 and LPDDR2 DRAM controller configurations | Andreas Hansson |
| 2013-01-31 | mem: Add tTAW and tFAW to the SimpleDRAM model | Ani Udipi |
| 2012-11-02 | sim: Include object header files in SWIG interfaces | Andreas Sandberg |
| 2012-09-21 | DRAM: Introduce SimpleDRAM to capture a high-level controller | Andreas Hansson |
