summaryrefslogtreecommitdiff
path: root/src/mem/bridge.cc
AgeCommit message (Expand)Author
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-07-14Merge of DPRINTF fixes from head.Steve Reinhardt
2007-07-14Fix & tweak DPRINTFs for tracediff w/new cache code.Steve Reinhardt
2007-06-30Don't propagate snoops across bridges. Wouldn't work anyway.Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-18Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
2007-05-13fix handling of atomic packetsAli Saidi
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ...Ali Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
2006-11-14Update bus bridges now that snoop ranges are passed properlyRon Dreslinski
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-13Fix for DMA's in FS caches.Ron Dreslinski
2006-08-14Fix up doxygen.Steve Reinhardt
2006-06-13Move SimObject creation and Port connection loopsSteve Reinhardt
2006-05-31Updated Authors from bk prs infoAli Saidi
2006-05-30Add a very poor implementation of dealing with retries on timing requests. It...Ali Saidi
2006-05-26Reorganize bridge as pair of cooperating ports.Steve Reinhardt
2006-05-22New directory structure:Steve Reinhardt