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path: root/src/mem/bridge.cc
AgeCommit message (Expand)Author
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-05-30Bridge: Split deferred request, response and sender stateAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Remove the notion of the default portAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-09-09mem: fix functional accesses to deal with coherence changeSteve Reinhardt
2009-11-18ruby: Added more info to bridge error messageBrad Beckmann
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-09-26When nesting if statements, use braces to avoid ambiguous else clauses.Nathan Binkert
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
2008-06-15port: Clean up default port setup and port switchover code.Nathan Binkert
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
2007-11-28Make ports that aren't connected to anything fail more gracefully.Gabe Black
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-26Merge with headGabe Black
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-07-14Merge of DPRINTF fixes from head.Steve Reinhardt
2007-07-14Fix & tweak DPRINTFs for tracediff w/new cache code.Steve Reinhardt
2007-06-30Don't propagate snoops across bridges. Wouldn't work anyway.Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-18Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
2007-05-13fix handling of atomic packetsAli Saidi
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ...Ali Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
2006-11-14Update bus bridges now that snoop ranges are passed properlyRon Dreslinski
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-13Fix for DMA's in FS caches.Ron Dreslinski
2006-08-14Fix up doxygen.Steve Reinhardt