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Author
2016-11-09
style: [patch 1/22] use /r/3648/ to reorganize includes
Brandon Potter
2016-02-10
mem: Move the point of coherency to the coherent crossbar
Andreas Hansson
2016-02-06
style: fix missing spaces in control statements
Steve Reinhardt
2015-12-31
mem: Make cache terminology easier to understand
Andreas Hansson
2015-11-06
mem: Use the packet delays and do not just zero them out
Andreas Hansson
2015-11-06
mem: Align rules for sinking inhibited packets at the slave
Andreas Hansson
2015-07-13
mem: Fix (ab)use of emplace to avoid temporary object creation
Andreas Hansson
2015-03-19
mem: Use emplace front/back for deferred packets
Andreas Hansson
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2015-02-11
mem: Clarification of packet crossbar timings
Marco Balboni
2015-01-22
mem: Remove unused RequestState in the bridge
Andreas Hansson
2014-12-02
mem: Relax packet src/dest check and shift onus to crossbar
Andreas Hansson
2014-09-20
mem: Rename Bus to XBar to better reflect its behaviour
Andreas Hansson
2013-07-18
mem: Set the cache line size on a system level
Andreas Hansson
2013-06-27
mem: Tidy up the bridge with const and additional checks
Andreas Hansson
2013-04-22
sim: separate nextCycle() and clockEdge() in clockedObjects
Dam Sunwoo
2013-02-19
mem: Enforce strict use of busFirst- and busLastWordTime
Andreas Hansson
2013-02-19
mem: Add predecessor to SenderState base class
Andreas Hansson
2012-10-15
Port: Add protocol-agnostic ports in the port hierarchy
Andreas Hansson
2012-09-19
AddrRange: Transition from Range<T> to AddrRange
Andreas Hansson
2012-08-28
Clock: Add a Cycles wrapper class and use where applicable
Andreas Hansson
2012-08-22
Bridge: Remove NACKs in the bridge and unify with packet queue
Andreas Hansson
2012-07-09
Port: Align port names in C++ and Python
Andreas Hansson
2012-07-09
Port: Make getAddrRanges const
Andreas Hansson
2012-05-30
Bridge: Split deferred request, response and sender state
Andreas Hansson
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-14
MEM: Remove the Broadcast destination from the packet
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-03-30
MEM: Introduce the master/slave port sub-classes in C++
William Wang
2012-02-24
MEM: Move port creation to the memory object(s) construction
Andreas Hansson
2012-01-17
MEM: Make the bus bridge unidirectional and fixed address range
Andreas Hansson
2012-01-17
MEM: Separate queries for snooping and address ranges
Andreas Hansson
2012-01-17
MEM: Remove the notion of the default port
Andreas Hansson
2012-01-17
MEM: Simplify ports by removing EventManager
Andreas Hansson
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2010-09-09
mem: fix functional accesses to deal with coherence change
Steve Reinhardt
2009-11-18
ruby: Added more info to bridge error message
Brad Beckmann
2008-10-09
eventq: convert all usage of events to use the new API.
Nathan Binkert
2008-09-26
When nesting if statements, use braces to avoid ambiguous else clauses.
Nathan Binkert
2008-06-28
Backed out changeset 94a7bb476fca: caused memory leak.
Steve Reinhardt
2008-06-21
Generate more useful error messages for unconnected ports.
Steve Reinhardt
2008-06-15
port: Clean up default port setup and port switchover code.
Nathan Binkert
2008-01-02
Add functional PrintReq command for memory-system debugging.
Steve Reinhardt
2007-11-28
Make ports that aren't connected to anything fail more gracefully.
Gabe Black
2007-08-30
params: Deprecate old-style constructors; update most SimObject constructors.
Miles Kaufmann
2007-08-26
Merge with head
Gabe Black
2007-08-10
DMA: Add IOCache and fix bus bridge to optionally only send requests one
Ali Saidi
2007-07-26
Merge python and x86 changes with cache branch
Nathan Binkert
2007-07-23
Major changes to how SimObjects are created and initialized. Almost all
Nathan Binkert
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