gem5 - gem5

Age	Commit message (Expand)	Author
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-22	Bridge: Remove NACKs in the bridge and unify with packet queue	Andreas Hansson
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-05-30	Bridge: Split deferred request, response and sender state	Andreas Hansson
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Remove the notion of the default port	Andreas Hansson
2012-01-17	MEM: Simplify ports by removing EventManager	Andreas Hansson
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-09-09	mem: fix functional accesses to deal with coherence change	Steve Reinhardt
2009-11-18	ruby: Added more info to bridge error message	Brad Beckmann
2008-10-09	eventq: convert all usage of events to use the new API.	Nathan Binkert
2008-09-26	When nesting if statements, use braces to avoid ambiguous else clauses.	Nathan Binkert
2008-06-28	Backed out changeset 94a7bb476fca: caused memory leak.	Steve Reinhardt
2008-06-21	Generate more useful error messages for unconnected ports.	Steve Reinhardt
2008-06-15	port: Clean up default port setup and port switchover code.	Nathan Binkert
2008-01-02	Add functional PrintReq command for memory-system debugging.	Steve Reinhardt
2007-11-28	Make ports that aren't connected to anything fail more gracefully.	Gabe Black
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-26	Merge with head	Gabe Black
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-07-14	Merge of DPRINTF fixes from head.	Steve Reinhardt
2007-07-14	Fix & tweak DPRINTFs for tracediff w/new cache code.	Steve Reinhardt
2007-06-30	Don't propagate snoops across bridges. Wouldn't work anyway.	Steve Reinhardt
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-06-17	More major reorg of cache. Seems to work for atomic mode now,	Steve Reinhardt
2007-05-22	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-05-21	Change getDeviceAddressRanges to use bool for snoop arg.	Steve Reinhardt
2007-05-18	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-05-18	First set of changes for reorganized cache coherence support.	Steve Reinhardt
2007-05-15	hopefully the final hacky change to make the bus bridge work ok	Ali Saidi
2007-05-13	fix handling of atomic packets	Ali Saidi
2007-05-09	add a backoff algorithm when nacks are received by devices	Ali Saidi
2007-05-07	the bridge never returns false when recvTiming() is called on its ports now, ...	Ali Saidi
2007-05-07	fix partial writes with a functional memory hack	Ali Saidi
2006-11-14	Update bus bridges now that snoop ranges are passed properly	Ron Dreslinski
2006-10-20	Use PacketPtr everywhere	Nathan Binkert
2006-10-13	Fix for DMA's in FS caches.	Ron Dreslinski
2006-08-14	Fix up doxygen.	Steve Reinhardt
2006-06-13	Move SimObject creation and Port connection loops	Steve Reinhardt