gem5 - gem5

Age	Commit message (Expand)	Author
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-07-14	Merge of DPRINTF fixes from head.	Steve Reinhardt
2007-07-14	Fix & tweak DPRINTFs for tracediff w/new cache code.	Steve Reinhardt
2007-06-30	Don't propagate snoops across bridges. Wouldn't work anyway.	Steve Reinhardt
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-06-17	More major reorg of cache. Seems to work for atomic mode now,	Steve Reinhardt
2007-05-22	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-05-21	Change getDeviceAddressRanges to use bool for snoop arg.	Steve Reinhardt
2007-05-18	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-05-18	First set of changes for reorganized cache coherence support.	Steve Reinhardt
2007-05-15	hopefully the final hacky change to make the bus bridge work ok	Ali Saidi
2007-05-13	fix handling of atomic packets	Ali Saidi
2007-05-09	add a backoff algorithm when nacks are received by devices	Ali Saidi
2007-05-07	the bridge never returns false when recvTiming() is called on its ports now, ...	Ali Saidi
2007-05-07	fix partial writes with a functional memory hack	Ali Saidi
2006-11-14	Update bus bridges now that snoop ranges are passed properly	Ron Dreslinski
2006-10-20	Use PacketPtr everywhere	Nathan Binkert
2006-10-13	Fix for DMA's in FS caches.	Ron Dreslinski
2006-08-14	Fix up doxygen.	Steve Reinhardt
2006-06-13	Move SimObject creation and Port connection loops	Steve Reinhardt
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-30	Add a very poor implementation of dealing with retries on timing requests. It...	Ali Saidi
2006-05-26	Reorganize bridge as pair of cooperating ports.	Steve Reinhardt
2006-05-22	New directory structure:	Steve Reinhardt