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path: root/src/mem/bridge.cc
AgeCommit message (Expand)Author
2017-06-20mem: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-11-06mem: Use the packet delays and do not just zero them outAndreas Hansson
2015-11-06mem: Align rules for sinking inhibited packets at the slaveAndreas Hansson
2015-07-13mem: Fix (ab)use of emplace to avoid temporary object creationAndreas Hansson
2015-03-19mem: Use emplace front/back for deferred packetsAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-01-22mem: Remove unused RequestState in the bridgeAndreas Hansson
2014-12-02mem: Relax packet src/dest check and shift onus to crossbarAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-06-27mem: Tidy up the bridge with const and additional checksAndreas Hansson
2013-04-22sim: separate nextCycle() and clockEdge() in clockedObjectsDam Sunwoo
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-05-30Bridge: Split deferred request, response and sender stateAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Remove the notion of the default portAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-09-09mem: fix functional accesses to deal with coherence changeSteve Reinhardt
2009-11-18ruby: Added more info to bridge error messageBrad Beckmann
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-09-26When nesting if statements, use braces to avoid ambiguous else clauses.Nathan Binkert
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
2008-06-15port: Clean up default port setup and port switchover code.Nathan Binkert
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
2007-11-28Make ports that aren't connected to anything fail more gracefully.Gabe Black
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-26Merge with headGabe Black
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
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