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path: root/src/mem/bridge.hh
AgeCommit message (Expand)Author
2008-03-24Don't FastAlloc MSHRs since we don't allocate them on the fly.Steve Reinhardt
2008-02-06Make the Event::description() a const functionStephen Hines
2007-08-26Merge with headGabe Black
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
2007-05-14add uglyiness to fix dmasAli Saidi
2007-05-13fix handling of atomic packetsAli Saidi
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ...Ali Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-08-14Fix up doxygen.Steve Reinhardt
2006-06-13Move SimObject creation and Port connection loopsSteve Reinhardt
2006-05-31Updated Authors from bk prs infoAli Saidi
2006-05-30Add a very poor implementation of dealing with retries on timing requests. It...Ali Saidi
2006-05-26Reorganize bridge as pair of cooperating ports.Steve Reinhardt
2006-05-26Add names to memory Port objects for tracing.Steve Reinhardt
2006-05-22New directory structure:Steve Reinhardt