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path: root/src/mem/bus.cc
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2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
Cleaning up and simplifying the ports and going towards a more strict elaboration-time creation and binding of the ports.
2012-01-09mem: Change DPRINTF prints more useful destination port number.Min Kyu Jeong
Old code prints 0 for destination since pkt->getDest() returns 0 for pkt->getDest() == Packet::Broadcast, which is always true.
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2010-08-17bus: clean up default responder code.Steve Reinhardt
Clean up some minor things left over from the default responder change in rev 9af6fb59752f. Mostly renaming the 'responder_set' param to 'use_default_range' to actually reflect what it does... old name wasn't that descriptive in the first place, but now it really doesn't make sense at all. Also got rid of the bogus obsolete assignment to 'bus.responder' which used to be a parameter but now is interpreted as an implicit child assignment, and which was giving me problems in the config restructuring to come. (A good argument for not allowing implicit child assignments, IMO, but that's water under the bridge, I'm afraid.) Also moved the Bus constructor to the .cc file since that's where it should have been all along.
2009-10-03bus: add assertion to catch illegal retrySteve Reinhardt
on mem-inhibited transaction.
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5.
2008-07-15Add missing newlines to Bus DPRINTFs.Steve Reinhardt
2008-06-28Automated merge after backout.Steve Reinhardt
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Make bus address conflict error more informativeSteve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
Force all non-default ports to provide a name and an owner in the constructor.
2008-03-17Restructure bus timing calcs to cope with pkt being deleted by target.Steve Reinhardt
--HG-- extra : convert_revision : db8497e73a44f2a06aab121e797e88b4c0c31330
2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
--HG-- extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc
2008-02-10Bus: Only update port cache when there is an item to update it with.Nicolas Zea
--HG-- extra : convert_revision : 84848fd48bb9e6693a0518c862364142b1969aa8
2008-02-06Make the Event::description() a const functionStephen Hines
--HG-- extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
2008-01-02Bug fix: functional cache port now needs otherPort set.Steve Reinhardt
--HG-- extra : convert_revision : fb007df73a77535a5dba19341f7b0b32e8c99548
2007-09-16mem: clean up bus/cache DPRINTFs a bitSteve Reinhardt
Not so much noise on failed sends, and more complete info when grepping a trace using an address. --HG-- extra : convert_revision : 05a8261c9452072ca08b906200c6322b33e2b9f1
2007-09-05Bus: Fix drain code; old method could return 1 in atomic mode and never call ↵Ali Saidi
de->process(). --HG-- extra : convert_revision : 35990e5eaf93f7a95a0ec72e9f92034a042def3e
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-26Merge with headGabe Black
--HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-12MemorySystem: Fix the use of ?: to produce correct results.Ali Saidi
--HG-- extra : convert_revision : 31aad7170b35556a4c984f4ebc013137d55d85eb
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-08-10Bus: Only call end() on an stl object once in a loopAli Saidi
--HG-- extra : convert_revision : 238dcd6da7577b533e52ada2107591c4e9168ebd
2007-08-04port: Implement cache for port interfaces and rangesVincentius Robby
--HG-- extra : convert_revision : d7cbec7c277fb8f4d8846203caae36ce629602d5
2007-07-29bus: take out response prioritization (timing was messed up).Steve Reinhardt
Also make express snoops not occupy bus (since they're magic). --HG-- extra : convert_revision : 75aa5211a59380026d1e3f122778425e48e2edcd
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
--HG-- extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-26bus: Fix default port handling.Steve Reinhardt
--HG-- extra : convert_revision : 121b6e31cddff17c51fc4f3df20e7e2bde87d04f
2007-07-24Integrate snoop loop functions into their respective call sites.Steve Reinhardt
Also some additional cleanup of Bus::recvTiming(). --HG-- extra : convert_revision : 156814119f75d04c2e954aec2d7ed6fdc186c26f
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-17Make sure responses never get blocked.Steve Reinhardt
--HG-- extra : convert_revision : 29f359d743994a94dc403aa0621ba72cd137d1a1
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
Atomic mode seems to work. Timing is closer but not there yet. --HG-- extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
2007-07-15Make Bus::findPort() a little more useful.Steve Reinhardt
Move check for loops outside, since half the call sites end up working around it anyway. Return integer port ID instead of port object pointer. --HG-- extra : convert_revision : 4c31fe9930f4d1aa4919e764efb7c50d43792ea3
2007-07-14Merge of DPRINTF fixes from head.Steve Reinhardt
--HG-- extra : convert_revision : f99a33b2df6a6c5592856d17d00e73ee83267442
2007-07-14Fix & tweak DPRINTFs for tracediff w/new cache code.Steve Reinhardt
Note that we should *not* print pointer values in DPRINTFs as these needlessly clutter tracediff output. --HG-- extra : convert_revision : 25a448f1b3ac8d453a717a104ad6dc0112fb30bb
2007-07-02bus.cc:Steve Reinhardt
Fix atomic timing issue. src/mem/bus.cc: Fix atomic timing issue. --HG-- extra : convert_revision : a22ff80cd75f83c785b0604c2a4fde2e2e9f71ef
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
now encoded in cmd field. --HG-- extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-21Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
2007-06-20Minor error.Vincentius Robby
--HG-- extra : convert_revision : 514032e21c8861f20fcbcae7204e132088cc7dbc
2007-06-20Removed "adding instead of dividing" trick.Vincentius Robby
Caused slowdown in performance instead of speeding up. src/cpu/base.cc: Removed "adding instead of dividing" trick. src/mem/bus.cc: Fixed spelling in comments. Removed "adding instead of dividing" trick. --HG-- extra : convert_revision : 65a736f4f09a64e737dc7aeee53b117976330488
2007-06-17Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 configs/example/memtest.py: Hand merge redundant changes. --HG-- extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. --HG-- extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-06-09Add a startup function that will fast forward to the right clock edgeNathan Binkert
using a divide in order to not loop forever after resuming from a checkpoint --HG-- extra : convert_revision : 4bbc70b1be4e5c4ed99d4f88418ab620d5ce475a
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 src/mem/cache/base_cache.hh: Manual conflict resolution. --HG-- extra : convert_revision : 5ebfd7abb4f978caa88bf43d25935869edfc6b9f
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
--HG-- extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
Compiles but doesn't work... committing just so I can merge (stupid bk!). src/mem/bridge.cc: Get rid of SNOOP_COMMIT. src/mem/bus.cc: src/mem/packet.hh: Get rid of SNOOP_COMMIT & two-pass snoop. First bits of EXPRESS_SNOOP support. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/prefetch/base_prefetcher.cc: Big reorg of ports and port-related functions & events. src/mem/cache/cache.cc: src/mem/cache/cache_builder.cc: src/mem/cache/coherence/SConscript: Get rid of UniCoherence object. --HG-- extra : convert_revision : 7672434fa3115c9b1c94686f497e57e90413b7c3
2007-05-09undo my previous bus change, it can make the bus deadlock.. so it still ↵Ali Saidi
constantly reschedules itself --HG-- extra : convert_revision : b5ef1aa0a6a2e32bd775d2dbcad9cd9505ad9b78
2007-05-07fix partial writes with a functional memory hackAli Saidi
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached configs/common/FSConfig.py: src/mem/bridge.cc: src/mem/bridge.hh: src/python/m5/objects/Bridge.py: fix partial writes with a functional memory hack src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached src/mem/packet.cc: fix WriteInvalidateResp to not be a request that needs a response since it isn't src/mem/port.hh: by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier --HG-- extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
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