gem5 - gem5

Age	Commit message (Expand)	Author
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-08-17	bus: clean up default responder code.	Steve Reinhardt
2009-10-03	bus: add assertion to catch illegal retry	Steve Reinhardt
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2008-07-16	mem: use single BadAddr responder per system.	Steve Reinhardt
2008-10-09	eventq: convert all usage of events to use the new API.	Nathan Binkert
2008-07-15	Add missing newlines to Bus DPRINTFs.	Steve Reinhardt
2008-06-28	Automated merge after backout.	Steve Reinhardt
2008-06-28	Backed out changeset 94a7bb476fca: caused memory leak.	Steve Reinhardt
2008-06-21	Make bus address conflict error more informative	Steve Reinhardt
2008-06-21	Generate more useful error messages for unconnected ports.	Steve Reinhardt
2008-03-17	Restructure bus timing calcs to cope with pkt being deleted by target.	Steve Reinhardt
2008-02-26	Bus: Fix the bus timing to be more realistic.	Gabe Black
2008-02-10	Bus: Only update port cache when there is an item to update it with.	Nicolas Zea
2008-02-06	Make the Event::description() a const function	Stephen Hines
2008-01-02	Bug fix: functional cache port now needs otherPort set.	Steve Reinhardt
2007-09-16	mem: clean up bus/cache DPRINTFs a bit	Steve Reinhardt
2007-09-05	Bus: Fix drain code; old method could return 1 in atomic mode and never call ...	Ali Saidi
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-26	Merge with head	Gabe Black
2007-08-12	MemorySystem: Fix the use of ?: to produce correct results.	Ali Saidi
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-08-10	Bus: Only call end() on an stl object once in a loop	Ali Saidi
2007-08-04	port: Implement cache for port interfaces and ranges	Vincentius Robby
2007-07-29	bus: take out response prioritization (timing was messed up).	Steve Reinhardt
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-26	bus: Fix default port handling.	Steve Reinhardt
2007-07-24	Integrate snoop loop functions into their respective call sites.	Steve Reinhardt
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-07-17	Make sure responses never get blocked.	Steve Reinhardt
2007-07-15	Fix up a bunch of multilevel coherence issues.	Steve Reinhardt
2007-07-15	Make Bus::findPort() a little more useful.	Steve Reinhardt
2007-07-14	Merge of DPRINTF fixes from head.	Steve Reinhardt
2007-07-14	Fix & tweak DPRINTFs for tracediff w/new cache code.	Steve Reinhardt
2007-07-02	bus.cc:	Steve Reinhardt
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-06-21	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-06-20	Minor error.	Vincentius Robby
2007-06-20	Removed "adding instead of dividing" trick.	Vincentius Robby
2007-06-17	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-06-17	More major reorg of cache. Seems to work for atomic mode now,	Steve Reinhardt
2007-06-09	Add a startup function that will fast forward to the right clock edge	Nathan Binkert
2007-05-22	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-05-21	Change getDeviceAddressRanges to use bool for snoop arg.	Steve Reinhardt
2007-05-18	First set of changes for reorganized cache coherence support.	Steve Reinhardt
2007-05-09	undo my previous bus change, it can make the bus deadlock.. so it still const...	Ali Saidi
2007-05-07	fix partial writes with a functional memory hack	Ali Saidi
2007-04-04	The MemoryObject tha owns a port should delete it if it so chooses when delet...	Ali Saidi
2007-03-23	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2007-03-23	3 memory system fixes:	Kevin Lim