summaryrefslogtreecommitdiff
path: root/src/mem/bus.cc
AgeCommit message (Expand)Author
2012-01-09mem: Change DPRINTF prints more useful destination port number.Min Kyu Jeong
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-08-17bus: clean up default responder code.Steve Reinhardt
2009-10-03bus: add assertion to catch illegal retrySteve Reinhardt
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-07-15Add missing newlines to Bus DPRINTFs.Steve Reinhardt
2008-06-28Automated merge after backout.Steve Reinhardt
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Make bus address conflict error more informativeSteve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
2008-03-17Restructure bus timing calcs to cope with pkt being deleted by target.Steve Reinhardt
2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
2008-02-10Bus: Only update port cache when there is an item to update it with.Nicolas Zea
2008-02-06Make the Event::description() a const functionStephen Hines
2008-01-02Bug fix: functional cache port now needs otherPort set.Steve Reinhardt
2007-09-16mem: clean up bus/cache DPRINTFs a bitSteve Reinhardt
2007-09-05Bus: Fix drain code; old method could return 1 in atomic mode and never call ...Ali Saidi
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-26Merge with headGabe Black
2007-08-12MemorySystem: Fix the use of ?: to produce correct results.Ali Saidi
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-10Bus: Only call end() on an stl object once in a loopAli Saidi
2007-08-04port: Implement cache for port interfaces and rangesVincentius Robby
2007-07-29bus: take out response prioritization (timing was messed up).Steve Reinhardt
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-26bus: Fix default port handling.Steve Reinhardt
2007-07-24Integrate snoop loop functions into their respective call sites.Steve Reinhardt
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-07-17Make sure responses never get blocked.Steve Reinhardt
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
2007-07-15Make Bus::findPort() a little more useful.Steve Reinhardt
2007-07-14Merge of DPRINTF fixes from head.Steve Reinhardt
2007-07-14Fix & tweak DPRINTFs for tracediff w/new cache code.Steve Reinhardt
2007-07-02bus.cc:Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-21Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-06-20Minor error.Vincentius Robby
2007-06-20Removed "adding instead of dividing" trick.Vincentius Robby
2007-06-17Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-06-09Add a startup function that will fast forward to the right clock edgeNathan Binkert
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
2007-05-09undo my previous bus change, it can make the bus deadlock.. so it still const...Ali Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
2007-04-04The MemoryObject tha owns a port should delete it if it so chooses when delet...Ali Saidi