gem5 - gem5

Age	Commit message (Expand)	Author
2008-01-02	Bug fix: functional cache port now needs otherPort set.	Steve Reinhardt
2007-09-16	mem: clean up bus/cache DPRINTFs a bit	Steve Reinhardt
2007-09-05	Bus: Fix drain code; old method could return 1 in atomic mode and never call ...	Ali Saidi
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-26	Merge with head	Gabe Black
2007-08-12	MemorySystem: Fix the use of ?: to produce correct results.	Ali Saidi
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-08-10	Bus: Only call end() on an stl object once in a loop	Ali Saidi
2007-08-04	port: Implement cache for port interfaces and ranges	Vincentius Robby
2007-07-29	bus: take out response prioritization (timing was messed up).	Steve Reinhardt
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-26	bus: Fix default port handling.	Steve Reinhardt
2007-07-24	Integrate snoop loop functions into their respective call sites.	Steve Reinhardt
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-07-17	Make sure responses never get blocked.	Steve Reinhardt
2007-07-15	Fix up a bunch of multilevel coherence issues.	Steve Reinhardt
2007-07-15	Make Bus::findPort() a little more useful.	Steve Reinhardt
2007-07-14	Merge of DPRINTF fixes from head.	Steve Reinhardt
2007-07-14	Fix & tweak DPRINTFs for tracediff w/new cache code.	Steve Reinhardt
2007-07-02	bus.cc:	Steve Reinhardt
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-06-21	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-06-20	Minor error.	Vincentius Robby
2007-06-20	Removed "adding instead of dividing" trick.	Vincentius Robby
2007-06-17	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-06-17	More major reorg of cache. Seems to work for atomic mode now,	Steve Reinhardt
2007-06-09	Add a startup function that will fast forward to the right clock edge	Nathan Binkert
2007-05-22	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2007-05-21	Change getDeviceAddressRanges to use bool for snoop arg.	Steve Reinhardt
2007-05-18	First set of changes for reorganized cache coherence support.	Steve Reinhardt
2007-05-09	undo my previous bus change, it can make the bus deadlock.. so it still const...	Ali Saidi
2007-05-07	fix partial writes with a functional memory hack	Ali Saidi
2007-04-04	The MemoryObject tha owns a port should delete it if it so chooses when delet...	Ali Saidi
2007-03-23	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2007-03-23	3 memory system fixes:	Kevin Lim
2007-03-08	stop m5 from leaking like a sieve	Ali Saidi
2007-02-06	More DPRINTF cleanup.	Steve Reinhardt
2007-02-06	Minor DPRINTF fixes.	Steve Reinhardt
2006-12-15	Use my range_map to speed up findPort() in the bus. The snoop code could stil...	Ali Saidi
2006-11-22	Do a functional access to levels above on a read as a temporary solution for ...	Ron Dreslinski
2006-11-14	Fix bugs around uni-coherence invalidates being propogated properly.	Ron Dreslinski
2006-11-14	Update atomic and functional paths for snoops as well	Ron Dreslinski
2006-11-14	Update bus bridges now that snoop ranges are passed properly	Ron Dreslinski
2006-11-13	Fix some errors related to snooping and functional access in the bus	Ron Dreslinski
2006-11-13	Fix problems with snoop ranges not working properly on functional accesses	Ron Dreslinski
2006-11-09	Be sure to populate the packet's finishTime field in the atomic timing case.	Kevin Lim
2006-11-09	Draining fixes.	Kevin Lim
2006-11-07	Fix up bus draining and add draining to the caches.	Kevin Lim
2006-11-02	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-11-02	Have bus use the BadAddress device to handle bad addresses. The O3 CPU shoul...	Kevin Lim