Age | Commit message (Collapse) | Author |
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Note that we should *not* print pointer values in DPRINTFs as
these needlessly clutter tracediff output.
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Caused slowdown in performance instead of speeding up.
src/cpu/base.cc:
Removed "adding instead of dividing" trick.
src/mem/bus.cc:
Fixed spelling in comments.
Removed "adding instead of dividing" trick.
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using a divide in order to not loop forever after resuming from a checkpoint
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constantly reschedules itself
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figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier
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deletePortRefs() is called on it with that port as a parameter.
In this way a MemoryObject can keep a functional port around and give it to anyone who wants to do functional accesses rather
than creating a new one each time.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/cache_impl.hh:
only keep around one func port we give to anyone who wants it. Otherwise we can run out of port ids reasonably quickly if
a lot of functional accesses are happening (e.g. remote debugging, dprintk, etc)
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extra : convert_revision : 6a9e3e96f51cedaab6de1b36cf317203899a3716
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
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extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
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1. Update packet's flags properly when a snoop happens
2. Don't allow accesses to read a block's data if the block has outstanding MSHRs. This avoids a RAW hazard in MP systems that the memory system was not detecting properly earlier (a write required a block to upgrade, and while the upgrade was outstanding, a read came along and read old data).
3. Update MSHR's request upon a response being handled. If the MSHR has more targets than it can respond to in one cycle, then its request must be properly updated to the new head of the targets list.
src/mem/bus.cc:
Update packet's flags properly upon snoop.
src/mem/cache/cache_impl.hh:
Be sure to not allow accesses to a block with outstanding MSHRs.
src/mem/cache/miss/miss_queue.cc:
Update MSHR's request upon a response being handled.
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extra : convert_revision : 76a9abc610ca3f1904f075ad21637148a41982d6
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don't create a new physPort/virtPort every time activateContext() is called
add the ability to tell a memory object to delete it's reference to a port and a method to have a port call deletePortRefs()
on the port owner as well as delete it's peer
still need to stop calling connectMemoPorts() every time activateContext() is called or we'll overflow the bus id and panic
src/cpu/thread_state.cc:
if we hav ea (phys|virt)Port don't create a new on, have it delete it's peer and then reuse it
src/mem/bus.cc:
src/mem/bus.hh:
add ability to delete a port by usig a hash_map instead of an array to store port ids
add a function to do deleting
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/mem_object.cc:
src/mem/mem_object.hh:
adda function to delete port references from a memory object
src/mem/port.cc:
src/mem/port.hh:
add a removeConn function that tell the owener to delete any references to the port and then deletes its peer
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still use some work.
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L2's in FS
Fix a small writeback bug when missing in the L2 in atomic mode
src/mem/bus.cc:
Fix a comment to make sense
src/mem/cache/cache_impl.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
Also fix a small writeback miss in L2 issue
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
Update ref's for writeback changes
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extra : convert_revision : 937febd577b16b7fd97a5a68acaf53541828a251
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src/mem/bus.cc:
Make it so that invalidates being sent from the responder up don't call the responder
but they should also not Panic.
src/mem/packet.hh:
If we don't have data in the packet, don't call deleteData:
Example: InvalidateRequests never have data.
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src/mem/bridge.cc:
Update brdiges, now that snoop addresses are properly forwarded.
Bus bridge should only handle snoops on the second phase (SNOOP_COMMIT)
src/mem/bus.cc:
src/mem/bus.hh:
Make sure if a busBridge has access to both things that snoop and things that respond it only takes the request once
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src/mem/bus.cc:
Only call snoop once per port, need to fix it so snoop ranges that overlap aren't added to list
Functional accesses that call snoop and it goes to a higher bus may change the src, reset it after each snoop.
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src/mem/bus.cc:
Actually return the snoop list when asked for it.
Don't get stuck in infinite functional loops
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src/cpu/o3/cpu.cc:
Handle draining properly when CPU isn't actually being used.
src/cpu/simple/atomic.cc:
Be sure to set status properly when draining.
src/mem/bus.cc:
Fix for draining.
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extra : convert_revision : d9796e6693e974f022159029fc9743c49a970c8f
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src/mem/bus.cc:
Fix up draining to work properly.
src/mem/bus.hh:
Initialize drainEvent to NULL.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Add draining to the caches.
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extra : convert_revision : 3082220a75d50876f10909f9f99bec535889f818
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
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should be able to boot into Linux with caches on after this change.
src/mem/bus.cc:
src/mem/bus.hh:
Bus now will be setup with a default responder, unless the user overrides it. This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
Bus now has a default responder for FS mode if the user doesn't override it. It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
Add bad address device. Also record when the user has specified their own default responder.
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Fix a segfault associated with DefaultId
src/mem/bus.cc:
Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
Make the Default ID more unique (it overlapped with Broadcast ID)
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src/mem/bus.cc:
Add debugging statement
src/mem/bus.hh:
Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
Rework timing port to retry properly
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src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
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case as well when dealing with grants that aren't used.
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some reason.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
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src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info
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try to send another packet while it's still waiting for the bus.
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src/mem/tport.cc:
minor formatting tweak
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src/mem/bus.cc:
Put back the check to see if the bus is busy. Also, populate the fields in the packet to indicate when the first word and the entire packet will be delivered.
src/mem/bus.hh:
Remove the occupyBus function.
src/mem/packet.hh:
Added fields to the packet to indicate when the first chunk of a packet arrives, and when the entire packet arrives.
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extra : convert_revision : cfc7670a33913d48a04d02c6d2448290a51f2d3c
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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src/mem/bus.cc:
Fixes to the previous hand merging, and put the snooping back into recvTiming and out of it's own function.
src/mem/bus.hh:
Put snooping back into recvTiming and not in it's own function.
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extra : convert_revision : fd031b7e6051a5be07ed6926454fde73b1739dc6
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If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
Make the fuctional path do the correct tye of snoop
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
src/mem/bus.cc:
Hand merged. Needs to be fixed
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code in general.
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src/mem/bus.cc:
src/mem/bus.hh:
minor fix and some formatting changes
src/python/m5/objects/Bus.py:
changed bits to bytes
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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Still need:
-Handle NACK's on the recieve side
-Distinguish top level caches
-Handle repsonses from caches failing the fast path
-Handle BusError and propogate it
-Fix the invalidate packet associated with snooping in the cache
src/mem/bus.cc:
Make sure to snoop on functional accesses
src/mem/cache/base_cache.cc:
Wait to make a request into a response until it is ready to be issued
src/mem/cache/base_cache.hh:
Support range changes for snoops
Set up snoop responses for cache->cache transfers
src/mem/cache/cache_impl.hh:
Only access the cache if it wasn't satisfied by cache->cache transfer
Handle snoop phases (detect block, then snoop)
Fix functional access to work properly (still need to fix snoop path for functional accesses)
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