gem5 - gem5

Age	Commit message (Expand)	Author
2012-05-08	MEM: Do not forward uncacheable to bus snoopers	Andreas Hansson
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-25	MEM: Use base class Master/SlavePort pointers in the bus	Andreas Hansson
2012-04-25	MEM: Add the PortId type and a corresponding id field to Port	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Unify bus access methods and prepare for master/slave split	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-24	MEM: Fatal when no port can be found for an address	Andreas Hansson
2012-02-09	MEM: Remove onRetryList from BusPort and rely on retryList	Andreas Hansson
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-17	MEM: Make the bus default port yet another port	Andreas Hansson
2012-01-17	MEM: Remove the functional ports from the memory system	William Wang
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Remove Port removeConn and MemObject deletePortRefs	Andreas Hansson
2012-01-09	mem: Change DPRINTF prints more useful destination port number.	Min Kyu Jeong
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-08-17	bus: clean up default responder code.	Steve Reinhardt
2009-10-03	bus: add assertion to catch illegal retry	Steve Reinhardt
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2008-07-16	mem: use single BadAddr responder per system.	Steve Reinhardt
2008-10-09	eventq: convert all usage of events to use the new API.	Nathan Binkert
2008-07-15	Add missing newlines to Bus DPRINTFs.	Steve Reinhardt
2008-06-28	Automated merge after backout.	Steve Reinhardt
2008-06-28	Backed out changeset 94a7bb476fca: caused memory leak.	Steve Reinhardt
2008-06-21	Make bus address conflict error more informative	Steve Reinhardt
2008-06-21	Generate more useful error messages for unconnected ports.	Steve Reinhardt
2008-03-17	Restructure bus timing calcs to cope with pkt being deleted by target.	Steve Reinhardt
2008-02-26	Bus: Fix the bus timing to be more realistic.	Gabe Black
2008-02-10	Bus: Only update port cache when there is an item to update it with.	Nicolas Zea
2008-02-06	Make the Event::description() a const function	Stephen Hines
2008-01-02	Bug fix: functional cache port now needs otherPort set.	Steve Reinhardt
2007-09-16	mem: clean up bus/cache DPRINTFs a bit	Steve Reinhardt
2007-09-05	Bus: Fix drain code; old method could return 1 in atomic mode and never call ...	Ali Saidi
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-26	Merge with head	Gabe Black
2007-08-12	MemorySystem: Fix the use of ?: to produce correct results.	Ali Saidi
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-08-10	Bus: Only call end() on an stl object once in a loop	Ali Saidi
2007-08-04	port: Implement cache for port interfaces and ranges	Vincentius Robby
2007-07-29	bus: take out response prioritization (timing was messed up).	Steve Reinhardt
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-26	bus: Fix default port handling.	Steve Reinhardt
2007-07-24	Integrate snoop loop functions into their respective call sites.	Steve Reinhardt
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-07-17	Make sure responses never get blocked.	Steve Reinhardt
2007-07-15	Fix up a bunch of multilevel coherence issues.	Steve Reinhardt
2007-07-15	Make Bus::findPort() a little more useful.	Steve Reinhardt