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path: root/src/mem/bus.hh
AgeCommit message (Expand)Author
2013-03-26mem: Separate waiting for the bus and waiting for a peerAndreas Hansson
2013-03-26mem: Introduce a variable for the retrying portAndreas Hansson
2013-03-01mem: Merge ranges in bus before passing them onAndreas Hansson
2013-02-19mem: Make packet bus-related time accounting relativeAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2013-01-07base: Encapsulate the underlying fields in AddrRangeAndreas Hansson
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Use deque instead of list for bus retriesAndreas Hansson
2012-10-15Mem: Use range operations in bus in preparation for stripingAndreas Hansson
2012-10-11Mem: Determine bus block size during initialisationAndreas Hansson
2012-09-21Mem: Tidy up bus member variables typesAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-07-09Bus: Split the bus into separate request/response layersAndreas Hansson
2012-07-09Bus: Add a notion of layers to the busesAndreas Hansson
2012-07-09Bus: Replace tickNextIdle and inRetry with a state variableAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-30Bus: Remove redundant packet parameter from isOccupiedAndreas Hansson
2012-05-30Bus: Turn the PortId into a transport function parameterAndreas Hansson
2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-25MEM: Use base class Master/SlavePort pointers in the busAndreas Hansson
2012-04-25MEM: Add the PortId type and a corresponding id field to PortAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Unify bus access methods and prepare for master/slave splitAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-24MEM: Fatal when no port can be found for an addressAndreas Hansson
2012-02-09MEM: Remove onRetryList from BusPort and rely on retryListAndreas Hansson
2012-01-17MEM: Make the bus default port yet another portAndreas Hansson
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
2011-04-15includes: sort all includesNathan Binkert
2010-08-17bus: clean up default responder code.Steve Reinhardt
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17includes: use base/types.hh not inttypes.h or stdint.hNathan Binkert
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
2008-03-17Restructure bus timing calcs to cope with pkt being deleted by target.Steve Reinhardt
2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
2008-02-06Make the Event::description() a const functionStephen Hines
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-08Port, StaticInst: Revert unnecessary changes.Vincentius Robby
2007-08-08alpha: Make the TLB cache to actually work.Vincentius Robby
2007-08-04port: Implement cache for port interfaces and rangesVincentius Robby