gem5 - gem5

Age	Commit message (Expand)	Author
2013-03-26	mem: Separate waiting for the bus and waiting for a peer	Andreas Hansson
2013-03-26	mem: Introduce a variable for the retrying port	Andreas Hansson
2013-03-01	mem: Merge ranges in bus before passing them on	Andreas Hansson
2013-02-19	mem: Make packet bus-related time accounting relative	Andreas Hansson
2013-02-19	sim: Make clock private and access using clockPeriod()	Andreas Hansson
2013-01-07	base: Encapsulate the underlying fields in AddrRange	Andreas Hansson
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Mem: Use deque instead of list for bus retries	Andreas Hansson
2012-10-15	Mem: Use range operations in bus in preparation for striping	Andreas Hansson
2012-10-11	Mem: Determine bus block size during initialisation	Andreas Hansson
2012-09-21	Mem: Tidy up bus member variables types	Andreas Hansson
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-07-09	Bus: Split the bus into separate request/response layers	Andreas Hansson
2012-07-09	Bus: Add a notion of layers to the buses	Andreas Hansson
2012-07-09	Bus: Replace tickNextIdle and inRetry with a state variable	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-05-30	Bus: Remove redundant packet parameter from isOccupied	Andreas Hansson
2012-05-30	Bus: Turn the PortId into a transport function parameter	Andreas Hansson
2012-05-30	Packet: Unify the use of PortID in packet and port	Andreas Hansson
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-25	MEM: Use base class Master/SlavePort pointers in the bus	Andreas Hansson
2012-04-25	MEM: Add the PortId type and a corresponding id field to Port	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Unify bus access methods and prepare for master/slave split	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-24	MEM: Fatal when no port can be found for an address	Andreas Hansson
2012-02-09	MEM: Remove onRetryList from BusPort and rely on retryList	Andreas Hansson
2012-01-17	MEM: Make the bus default port yet another port	Andreas Hansson
2012-01-17	MEM: Remove the functional ports from the memory system	William Wang
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Remove Port removeConn and MemObject deletePortRefs	Andreas Hansson
2011-04-15	includes: sort all includes	Nathan Binkert
2010-08-17	bus: clean up default responder code.	Steve Reinhardt
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2009-05-17	includes: sort includes again	Nathan Binkert
2009-05-17	includes: use base/types.hh not inttypes.h or stdint.h	Nathan Binkert
2008-06-28	Backed out changeset 94a7bb476fca: caused memory leak.	Steve Reinhardt
2008-06-21	Generate more useful error messages for unconnected ports.	Steve Reinhardt
2008-03-17	Restructure bus timing calcs to cope with pkt being deleted by target.	Steve Reinhardt
2008-02-26	Bus: Fix the bus timing to be more realistic.	Gabe Black
2008-02-06	Make the Event::description() a const function	Stephen Hines
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-08-08	Port, StaticInst: Revert unnecessary changes.	Vincentius Robby
2007-08-08	alpha: Make the TLB cache to actually work.	Vincentius Robby
2007-08-04	port: Implement cache for port interfaces and ranges	Vincentius Robby