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path: root/src/mem/cache/BaseCache.py
AgeCommit message (Expand)Author
2013-01-07mem: Remove the IIC replacement policyAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2010-02-23cache: Make caches sharing aware and add occupancy stats.Lisa Hsu
2009-09-26Force prefetches to check cache and MSHRs immediately prior to issue.Steve Reinhardt
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
2009-02-16Fixes to get prefetching working again.Steve Reinhardt
2008-10-23remove the totally obsolete split cacheLisa Hsu
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-03cache: get rid of obsolete params from python.Steve Reinhardt
2007-06-30Get rid of remaining traces of obsolete CoherenceProtocol object.Steve Reinhardt
2007-06-20Make sure all parameters have default values if they'reNathan Binkert
2007-06-09More realistic parametersNathan Binkert
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert