gem5 - gem5

Age	Commit message (Expand)	Author
2014-01-24	Cache: Collect very basic stats on tag and data accesses	Timothy M. Jones
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-06-27	mem: Reorganize cache tags and make them a SimObject	Prakash Ramrakhyani
2013-01-07	mem: Remove the IIC replacement policy	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: fix cache stats to use request ids correctly	Dam Sunwoo
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2010-02-23	cache: Make caches sharing aware and add occupancy stats.	Lisa Hsu
2009-09-26	Force prefetches to check cache and MSHRs immediately prior to issue.	Steve Reinhardt
2008-07-16	mem: use single BadAddr responder per system.	Steve Reinhardt
2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
2008-10-23	remove the totally obsolete split cache	Lisa Hsu
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-08-03	cache: get rid of obsolete params from python.	Steve Reinhardt
2007-06-30	Get rid of remaining traces of obsolete CoherenceProtocol object.	Steve Reinhardt
2007-06-20	Make sure all parameters have default values if they're	Nathan Binkert
2007-06-09	More realistic parameters	Nathan Binkert
2007-05-27	Move SimObject python files alongside the C++ and fix	Nathan Binkert