gem5 - gem5

Age	Commit message (Expand)	Author
2018-06-14	base,mem: Support AtomicOpFunctor in the classic memory system	Tuan Ta
2018-06-13	mem-cache: Insert on block allocation	Daniel R. Carvalho
2018-06-11	misc: Using smart pointers for memory Requests	Giacomo Travaglini
2018-06-11	misc: Substitute pointer to Request with aliased RequestPtr	Giacomo Travaglini
2018-06-08	mem-cache: Change Cache block tag check	Daniel R. Carvalho
2018-06-08	mem-cache: Use secure bit in findVictim	Daniel R. Carvalho
2018-06-08	mem-cache: Return evictions along with victims	Daniel R. Carvalho
2018-06-01	mem-cache: Create an address aware TempCacheBlk	Daniel R. Carvalho
2018-06-01	mem-cache: Fix secure bit modification	Daniel R. Carvalho
2018-05-31	mem-cache: Replace block visitor with std::function	Nikos Nikoleris
2018-05-31	mem-cache: Move cache bypass mechanism to the ports	Nikos Nikoleris
2018-05-31	mem-cache: Adopt a more sensible cache class hierarchy	Nikos Nikoleris
2018-05-17	mem-cache: Move replacements stat to the base cache class	Nikos Nikoleris
2018-03-22	mem-cache: Split array indexing and replacement policies.	Daniel R. Carvalho
2017-06-20	mem: Replace EventWrapper use with EventFunctionWrapper	Sean Wilson
2016-11-30	mem: Split the hit_latency into tag_latency and data_latency	Sophiane Senni
2016-06-06	sim: Call regStats of base-class as well	Stephan Diestelhorst
2016-05-26	mem: fix headers include order in the cache related classes	Nikos Nikoleris
2016-05-26	mem: change NULL to nullptr in the cache related classes	Nikos Nikoleris
2016-05-26	mem: fix the line length in the cache related classes	Nikos Nikoleris
2016-04-21	mem: Include WriteLineReq in cache demand stats	Andreas Hansson
2016-04-21	mem: Remove unused cache stats	Andreas Hansson
2015-05-27	mem: Add unused prefetch counter in caches	Rekai Gonzalez Alberquilla
2016-03-17	mem: Adjust cache queue reserve to more conservative values	Andreas Hansson
2016-03-17	mem: Create a separate class for the cache write buffer	Andreas Hansson
2016-02-10	mem: Deduce if cache should forward snoops	Andreas Hansson
2015-08-21	mem: Add explicit Cache subclass and make BaseCache abstract	Andreas Hansson
2015-07-07	sim: Decouple draining from the SimObject hierarchy	Andreas Sandberg
2015-07-07	sim: Make the drain state a global typed enum	Andreas Sandberg
2015-07-03	mem: Remove redundant is_top_level cache parameter	Andreas Hansson
2015-07-03	mem: Add ReadCleanReq and ReadSharedReq packets	Andreas Hansson
2015-07-03	mem: Allow read-only caches and check compliance	Andreas Hansson
2015-05-05	mem: Snoop into caches on uncacheable accesses	Andreas Hansson
2015-05-05	mem: Remove templates in cache model	David Guillen
2015-03-02	mem: Tidy up the cache debug messages	Andreas Hansson
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-02-11	mem: Clarify usage of latency in the cache	Marco Balboni
2014-12-23	mem: Add parameter to reserve MSHR entries for demand access	Mitch Hayenga
2014-09-09	misc: Fix a number of unitialised variables and members	Andreas Hansson
2014-06-27	mem: write streaming support via WriteInvalidate promotion	Curtis Dunham
2014-09-03	mem: Fix a bug in the cache port flow control	Andreas Hansson
2014-07-28	mem: refactor LRU cache tags and add random replacement tags	Anthony Gutierrez
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-06-27	mem: Reorganize cache tags and make them a SimObject	Prakash Ramrakhyani
2013-06-27	mem: Remove the cache builder	Andreas Hansson
2013-03-26	mem: Cancel cache retry event when blocking port	Rene de Jong
2013-01-28	cache: remove drainManager because it's not used	Anthony Gutierrez
2013-01-07	sim: Fatal if a clocked object is set to have a clock of 0	Andreas Hansson
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg