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base.cc
Age
Commit message (
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Author
2016-03-17
mem: Adjust cache queue reserve to more conservative values
Andreas Hansson
2016-03-17
mem: Create a separate class for the cache write buffer
Andreas Hansson
2016-02-10
mem: Deduce if cache should forward snoops
Andreas Hansson
2015-08-21
mem: Add explicit Cache subclass and make BaseCache abstract
Andreas Hansson
2015-07-07
sim: Decouple draining from the SimObject hierarchy
Andreas Sandberg
2015-07-07
sim: Make the drain state a global typed enum
Andreas Sandberg
2015-07-03
mem: Remove redundant is_top_level cache parameter
Andreas Hansson
2015-07-03
mem: Add ReadCleanReq and ReadSharedReq packets
Andreas Hansson
2015-07-03
mem: Allow read-only caches and check compliance
Andreas Hansson
2015-05-05
mem: Snoop into caches on uncacheable accesses
Andreas Hansson
2015-05-05
mem: Remove templates in cache model
David Guillen
2015-03-02
mem: Tidy up the cache debug messages
Andreas Hansson
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2015-02-11
mem: Clarify usage of latency in the cache
Marco Balboni
2014-12-23
mem: Add parameter to reserve MSHR entries for demand access
Mitch Hayenga
2014-09-09
misc: Fix a number of unitialised variables and members
Andreas Hansson
2014-06-27
mem: write streaming support via WriteInvalidate promotion
Curtis Dunham
2014-09-03
mem: Fix a bug in the cache port flow control
Andreas Hansson
2014-07-28
mem: refactor LRU cache tags and add random replacement tags
Anthony Gutierrez
2013-09-04
arch: Resurrect the NOISA build target and rename it NULL
Andreas Hansson
2013-07-18
mem: Set the cache line size on a system level
Andreas Hansson
2013-06-27
mem: Reorganize cache tags and make them a SimObject
Prakash Ramrakhyani
2013-06-27
mem: Remove the cache builder
Andreas Hansson
2013-03-26
mem: Cancel cache retry event when blocking port
Rene de Jong
2013-01-28
cache: remove drainManager because it's not used
Anthony Gutierrez
2013-01-07
sim: Fatal if a clocked object is set to have a clock of 0
Andreas Hansson
2012-11-02
mem: Add support for writing back and flushing caches
Andreas Sandberg
2012-11-02
sim: Move the draining interface into a separate base class
Andreas Sandberg
2012-10-15
Port: Add protocol-agnostic ports in the port hierarchy
Andreas Hansson
2012-10-15
Mem: Use cycles to express cache-related latencies
Andreas Hansson
2012-09-25
Cache: add a response latency to the caches
Mrinmoy Ghosh
2012-08-15
O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...
Anthony Gutierrez
2012-03-30
MEM: Introduce the master/slave port sub-classes in C++
William Wang
2012-03-22
MEM: Split SimpleTimingPort into PacketQueue and ports
Andreas Hansson
2012-03-09
cache: Allow main memory to be at disjoint address ranges.
Ali Saidi
2012-02-24
MEM: Simplify cache ports preparing for master/slave split
Andreas Hansson
2012-02-12
mem: fix cache stats to use request ids correctly
Dam Sunwoo
2012-01-31
Merge with head, hopefully the last time for this batch.
Gabe Black
2012-01-31
MEM: Remove the otherPort from the cache ports
Andreas Hansson
2012-01-28
Merge with the main repo.
Gabe Black
2012-01-17
MEM: Separate queries for snooping and address ranges
Andreas Hansson
2012-01-17
MEM: Simplify ports by removing EventManager
Andreas Hansson
2011-11-07
SE/FS: Get rid of FULL_SYSTEM in mem.
Gabe Black
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2011-03-17
Mem: Fix issue with dirty block being lost when entire block transferred to n...
Ali Saidi
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2010-02-23
cache: Make caches sharing aware and add occupancy stats.
Lisa Hsu
2009-06-04
types: clean up types, especially signed vs unsigned
Nathan Binkert
2008-07-16
mem: use single BadAddr responder per system.
Steve Reinhardt
2008-10-09
eventq: convert all usage of events to use the new API.
Nathan Binkert
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