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path: root/src/mem/cache/base.cc
AgeCommit message (Expand)Author
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
2015-07-03mem: Add ReadCleanReq and ReadSharedReq packetsAndreas Hansson
2015-07-03mem: Allow read-only caches and check complianceAndreas Hansson
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-05-05mem: Remove templates in cache modelDavid Guillen
2015-03-02mem: Tidy up the cache debug messagesAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2014-12-23mem: Add parameter to reserve MSHR entries for demand accessMitch Hayenga
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
2014-06-27mem: write streaming support via WriteInvalidate promotionCurtis Dunham
2014-09-03mem: Fix a bug in the cache port flow controlAndreas Hansson
2014-07-28mem: refactor LRU cache tags and add random replacement tagsAnthony Gutierrez
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-06-27mem: Reorganize cache tags and make them a SimObjectPrakash Ramrakhyani
2013-06-27mem: Remove the cache builderAndreas Hansson
2013-03-26mem: Cancel cache retry event when blocking portRene de Jong
2013-01-28cache: remove drainManager because it's not usedAnthony Gutierrez
2013-01-07sim: Fatal if a clocked object is set to have a clock of 0Andreas Hansson
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31MEM: Remove the otherPort from the cache portsAndreas Hansson
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
2011-11-07SE/FS: Get rid of FULL_SYSTEM in mem.Gabe Black
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-02-23cache: Make caches sharing aware and add occupancy stats.Lisa Hsu
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt