Age | Commit message (Expand) | Author |
2019-08-28 | mem: Eliminate the Base(Slave|Master)Port classes. | Gabe Black |
2019-06-04 | Revert "mem-cache: Remove writebacks packet list" | Daniel Carvalho |
2019-05-18 | arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code. | Gabe Black |
2019-05-08 | mem-cache: Remove writebacks packet list | Daniel R. Carvalho |
2019-05-08 | mem-cache: Handle data expansion | Daniel R. Carvalho |
2019-05-08 | mem-cache: Add compression and decompression calls | Daniel R. Carvalho |
2019-04-28 | mem: Minimize the use of MemObject. | Gabe Black |
2019-04-19 | mem: Add packet matching functions | Daniel R. Carvalho |
2019-03-19 | arch, cpu, dev, gpu, mem, sim, python: start using getPort. | Gabe Black |
2019-03-07 | mem-cache: Allow tag-only accesses on latency calculation | Daniel R. Carvalho |
2019-03-07 | mem-cache: Use header delay on latency calculation | Daniel R. Carvalho |
2019-02-25 | mem-cache: A Best-Offset Prefetcher | Ivan Pizarro |
2019-02-01 | mem-cache: Updated version of the Signature Path Prefetcher | Javier Bueno |
2018-12-05 | mem-cache: Remove writebacks parameter from serviceMSHRTargets | Daniel R. Carvalho |
2018-11-14 | mem-cache: Move access latency calculation to Cache | Daniel R. Carvalho |
2018-11-14 | mem-cache: implement a probe-based interface | Javier Bueno |
2018-10-22 | mem-cache: Move evictBlock(CacheBlk*, PacketList&) to base | Daniel R. Carvalho |
2018-10-18 | mem: Add write coalescing and write-no-allocate to the caches | Nikos Nikoleris |
2018-10-18 | mem: Restructure whole-line writes to simplify write merging | Nikos Nikoleris |
2018-10-11 | mem-cache: Rename blk.cc/hh to cache_blk.cc/hh | Daniel R. Carvalho |
2018-09-13 | mem-cache: Fix bug in handleAtomicReqMiss | Nikos Nikoleris |
2018-06-13 | mem-cache: Insert on block allocation | Daniel R. Carvalho |
2018-06-01 | mem-cache: Create an address aware TempCacheBlk | Daniel R. Carvalho |
2018-05-31 | mem-cache: Replace block visitor with std::function | Nikos Nikoleris |
2018-05-31 | mem-cache: Adopt a more sensible cache class hierarchy | Nikos Nikoleris |
2018-05-17 | mem-cache: Move replacements stat to the base cache class | Nikos Nikoleris |
2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
2017-06-27 | mem-cache: Add missing overrides to BaseCache | Andreas Sandberg |
2017-06-20 | mem: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
2017-03-03 | mem: Use pkt::getBlockAddr instead of BaseCace::blockAlign | Nikos Nikoleris |
2016-12-05 | mem: Make packet debug printing more uniform | Nikos Nikoleris |
2016-11-30 | mem: Split the hit_latency into tag_latency and data_latency | Sophiane Senni |
2016-05-26 | mem: fix the line length in the cache related classes | Nikos Nikoleris |
2016-04-21 | mem: Remove unused cache stats | Andreas Hansson |
2015-05-27 | mem: Add unused prefetch counter in caches | Rekai Gonzalez Alberquilla |
2016-03-17 | mem: Create a separate class for the cache write buffer | Andreas Hansson |
2016-02-10 | mem: Deduce if cache should forward snoops | Andreas Hansson |
2015-12-31 | mem: Make cache terminology easier to understand | Andreas Hansson |
2015-11-06 | mem: Add an option to perform clean writebacks from caches | Andreas Hansson |
2015-11-06 | mem: Add cache clusivity | Andreas Hansson |
2015-11-06 | mem: Do not treat CleanEvict as a write operation | Andreas Hansson |
2015-08-21 | mem: Add explicit Cache subclass and make BaseCache abstract | Andreas Hansson |
2015-08-21 | mem: Move cache_impl.hh to cache.cc | Andreas Hansson |
2015-07-30 | mem: Remove unused RequestCause in cache | Andreas Hansson |
2015-07-07 | sim: Decouple draining from the SimObject hierarchy | Andreas Sandberg |
2015-07-03 | mem: Remove redundant is_top_level cache parameter | Andreas Hansson |
2015-07-03 | mem: Allow read-only caches and check compliance | Andreas Hansson |
2015-05-05 | mem: Snoop into caches on uncacheable accesses | Andreas Hansson |
2015-03-27 | mem: Remove redundant allocateUncachedReadBuffer in cache | Andreas Hansson |
2015-03-27 | mem: Align all MSHR entries to block boundaries | Andreas Hansson |