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path: root/src/mem/cache/base.hh
AgeCommit message (Expand)Author
2017-06-27mem-cache: Add missing overrides to BaseCacheAndreas Sandberg
2017-06-20mem: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-03-03mem: Use pkt::getBlockAddr instead of BaseCace::blockAlignNikos Nikoleris
2016-12-05mem: Make packet debug printing more uniformNikos Nikoleris
2016-11-30mem: Split the hit_latency into tag_latency and data_latencySophiane Senni
2016-05-26mem: fix the line length in the cache related classesNikos Nikoleris
2016-04-21mem: Remove unused cache statsAndreas Hansson
2015-05-27mem: Add unused prefetch counter in cachesRekai Gonzalez Alberquilla
2016-03-17mem: Create a separate class for the cache write bufferAndreas Hansson
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-11-06mem: Add an option to perform clean writebacks from cachesAndreas Hansson
2015-11-06mem: Add cache clusivityAndreas Hansson
2015-11-06mem: Do not treat CleanEvict as a write operationAndreas Hansson
2015-08-21mem: Add explicit Cache subclass and make BaseCache abstractAndreas Hansson
2015-08-21mem: Move cache_impl.hh to cache.ccAndreas Hansson
2015-07-30mem: Remove unused RequestCause in cacheAndreas Hansson
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
2015-07-03mem: Allow read-only caches and check complianceAndreas Hansson
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-03-27mem: Remove redundant allocateUncachedReadBuffer in cacheAndreas Hansson
2015-03-27mem: Align all MSHR entries to block boundariesAndreas Hansson
2015-03-02mem: Tidy up the cache debug messagesAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2015-02-03mem: Clarify cache behaviour for pending dirty responsesAndreas Hansson
2014-12-02mem: Remove WriteInvalidate supportCurtis Dunham
2014-06-27mem: write streaming support via WriteInvalidate promotionCurtis Dunham
2014-09-03mem: Fix a bug in the cache port flow controlAndreas Hansson
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2013-02-15mem: Tighten up cache constness and scopingAndreas Hansson
2013-01-28cache: remove drainManager because it's not usedAnthony Gutierrez
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
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