| Age | Commit message (Expand) | Author |
|---|
| 2018-06-13 | mem-cache: Insert on block allocation | Daniel R. Carvalho |
| 2018-06-01 | mem-cache: Create an address aware TempCacheBlk | Daniel R. Carvalho |
| 2018-05-31 | mem-cache: Replace block visitor with std::function | Nikos Nikoleris |
| 2018-05-31 | mem-cache: Adopt a more sensible cache class hierarchy | Nikos Nikoleris |
| 2018-05-17 | mem-cache: Move replacements stat to the base cache class | Nikos Nikoleris |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-06-27 | mem-cache: Add missing overrides to BaseCache | Andreas Sandberg |
| 2017-06-20 | mem: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
| 2017-03-03 | mem: Use pkt::getBlockAddr instead of BaseCace::blockAlign | Nikos Nikoleris |
| 2016-12-05 | mem: Make packet debug printing more uniform | Nikos Nikoleris |
| 2016-11-30 | mem: Split the hit_latency into tag_latency and data_latency | Sophiane Senni |
| 2016-05-26 | mem: fix the line length in the cache related classes | Nikos Nikoleris |
| 2016-04-21 | mem: Remove unused cache stats | Andreas Hansson |
| 2015-05-27 | mem: Add unused prefetch counter in caches | Rekai Gonzalez Alberquilla |
| 2016-03-17 | mem: Create a separate class for the cache write buffer | Andreas Hansson |
| 2016-02-10 | mem: Deduce if cache should forward snoops | Andreas Hansson |
| 2015-12-31 | mem: Make cache terminology easier to understand | Andreas Hansson |
| 2015-11-06 | mem: Add an option to perform clean writebacks from caches | Andreas Hansson |
| 2015-11-06 | mem: Add cache clusivity | Andreas Hansson |
| 2015-11-06 | mem: Do not treat CleanEvict as a write operation | Andreas Hansson |
| 2015-08-21 | mem: Add explicit Cache subclass and make BaseCache abstract | Andreas Hansson |
| 2015-08-21 | mem: Move cache_impl.hh to cache.cc | Andreas Hansson |
| 2015-07-30 | mem: Remove unused RequestCause in cache | Andreas Hansson |
| 2015-07-07 | sim: Decouple draining from the SimObject hierarchy | Andreas Sandberg |
| 2015-07-03 | mem: Remove redundant is_top_level cache parameter | Andreas Hansson |
| 2015-07-03 | mem: Allow read-only caches and check compliance | Andreas Hansson |
| 2015-05-05 | mem: Snoop into caches on uncacheable accesses | Andreas Hansson |
| 2015-03-27 | mem: Remove redundant allocateUncachedReadBuffer in cache | Andreas Hansson |
| 2015-03-27 | mem: Align all MSHR entries to block boundaries | Andreas Hansson |
| 2015-03-02 | mem: Tidy up the cache debug messages | Andreas Hansson |
| 2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
| 2015-02-11 | mem: Clarify usage of latency in the cache | Marco Balboni |
| 2015-02-03 | mem: Clarify cache behaviour for pending dirty responses | Andreas Hansson |
| 2014-12-02 | mem: Remove WriteInvalidate support | Curtis Dunham |
| 2014-06-27 | mem: write streaming support via WriteInvalidate promotion | Curtis Dunham |
| 2014-09-03 | mem: Fix a bug in the cache port flow control | Andreas Hansson |
| 2014-01-24 | mem: Add support for a security bit in the memory system | Giacomo Gabrielli |
| 2014-01-24 | mem: track per-request latencies and access depths in the cache hierarchy | Matt Horsnell |
| 2013-02-15 | mem: Tighten up cache constness and scoping | Andreas Hansson |
| 2013-01-28 | cache: remove drainManager because it's not used | Anthony Gutierrez |
| 2012-11-02 | mem: Add support for writing back and flushing caches | Andreas Sandberg |
| 2012-11-02 | sim: Move the draining interface into a separate base class | Andreas Sandberg |
| 2012-10-15 | Port: Add protocol-agnostic ports in the port hierarchy | Andreas Hansson |
| 2012-10-15 | Mem: Use cycles to express cache-related latencies | Andreas Hansson |
| 2012-09-25 | Cache: add a response latency to the caches | Mrinmoy Ghosh |
| 2012-08-22 | Port: Extend the QueuedPort interface and use where appropriate | Andreas Hansson |
| 2012-07-09 | Port: Move retry from port base class to Master/SlavePort | Andreas Hansson |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
