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base.hh
Age
Commit message (
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Author
2015-07-03
mem: Remove redundant is_top_level cache parameter
Andreas Hansson
2015-07-03
mem: Allow read-only caches and check compliance
Andreas Hansson
2015-05-05
mem: Snoop into caches on uncacheable accesses
Andreas Hansson
2015-03-27
mem: Remove redundant allocateUncachedReadBuffer in cache
Andreas Hansson
2015-03-27
mem: Align all MSHR entries to block boundaries
Andreas Hansson
2015-03-02
mem: Tidy up the cache debug messages
Andreas Hansson
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2015-02-11
mem: Clarify usage of latency in the cache
Marco Balboni
2015-02-03
mem: Clarify cache behaviour for pending dirty responses
Andreas Hansson
2014-12-02
mem: Remove WriteInvalidate support
Curtis Dunham
2014-06-27
mem: write streaming support via WriteInvalidate promotion
Curtis Dunham
2014-09-03
mem: Fix a bug in the cache port flow control
Andreas Hansson
2014-01-24
mem: Add support for a security bit in the memory system
Giacomo Gabrielli
2014-01-24
mem: track per-request latencies and access depths in the cache hierarchy
Matt Horsnell
2013-02-15
mem: Tighten up cache constness and scoping
Andreas Hansson
2013-01-28
cache: remove drainManager because it's not used
Anthony Gutierrez
2012-11-02
mem: Add support for writing back and flushing caches
Andreas Sandberg
2012-11-02
sim: Move the draining interface into a separate base class
Andreas Sandberg
2012-10-15
Port: Add protocol-agnostic ports in the port hierarchy
Andreas Hansson
2012-10-15
Mem: Use cycles to express cache-related latencies
Andreas Hansson
2012-09-25
Cache: add a response latency to the caches
Mrinmoy Ghosh
2012-08-22
Port: Extend the QueuedPort interface and use where appropriate
Andreas Hansson
2012-07-09
Port: Move retry from port base class to Master/SlavePort
Andreas Hansson
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-03-30
MEM: Introduce the master/slave port sub-classes in C++
William Wang
2012-03-22
MEM: Split SimpleTimingPort into PacketQueue and ports
Andreas Hansson
2012-03-09
cache: Allow main memory to be at disjoint address ranges.
Ali Saidi
2012-02-24
MEM: Simplify cache ports preparing for master/slave split
Andreas Hansson
2012-02-12
mem: fix cache stats to use request ids correctly
Dam Sunwoo
2012-01-31
Merge with head, hopefully the last time for this batch.
Gabe Black
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2012-01-31
MEM: Remove the otherPort from the cache ports
Andreas Hansson
2012-01-28
Merge with the main repo.
Gabe Black
2012-01-17
MEM: Separate queries for snooping and address ranges
Andreas Hansson
2011-11-18
SE/FS: Get rid of includes of config/full_system.hh.
Gabe Black
2011-11-07
SE/FS: Get rid of FULL_SYSTEM in mem.
Gabe Black
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2011-04-15
includes: sort all includes
Nathan Binkert
2011-03-17
Mem: Fix issue with dirty block being lost when entire block transferred to n...
Ali Saidi
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2010-09-10
style: fix sorting of includes and whitespace in some files
Nathan Binkert
2010-09-09
cache: coherence protocol enhancements & bug fixes
Steve Reinhardt
2010-06-15
stats: only consider a formula initialized if there is a formula
Nathan Binkert
2010-02-23
cache: Make caches sharing aware and add occupancy stats.
Lisa Hsu
2009-09-26
Minor cleanup: Use the blockAlign() method where it applies in the cache.
Steve Reinhardt
2009-06-04
types: clean up types, especially signed vs unsigned
Nathan Binkert
2009-05-17
includes: use base/types.hh not inttypes.h or stdint.h
Nathan Binkert
2008-07-16
mem: use single BadAddr responder per system.
Steve Reinhardt
2009-03-05
stats: Fix all stats usages to deal with template fixes
Nathan Binkert
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