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2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
--HG-- rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
--HG-- extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-07-29memory system: fix functional access bug.Steve Reinhardt
Make sure not to keep processing functional accesses after they've been responded to. Also use checkFunctional() return value instead of checking packet command field where possible, mostly just for consistency. --HG-- extra : convert_revision : 29fc76bc18731bd93a4ed05a281297827028ef75
2007-06-30Fix up a few statistics problems.Steve Reinhardt
Stats pretty much line up with old code, except: - bug in old code included L1 latency in L2 miss time, making it too high - UniCoherence did cache-to-cache transfers even from non-owner caches, so occasionally the icache would get a block from the dcache not the L2 - L2 can now receive ReadExReq from L1 since L1s have coherence --HG-- extra : convert_revision : 5052c1a1767b5a662f30a88f16012165a73b791c
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
now encoded in cmd field. --HG-- extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-25Get rid of requestCauses. Use timestamped queue to makeSteve Reinhardt
sure we don't re-request bus prematurely. Use callback to avoid calling sendRetry() recursively within recvTiming. --HG-- extra : convert_revision : a907a2781b4b00aa8eb1ea7147afc81d6b424140
2007-06-24Better handling of deferred targets.Steve Reinhardt
--HG-- extra : convert_revision : 0fbc28c32c1eeb3dd672df14c1d53bd516f81d0f
2007-06-22Fixes to hitLatency, blocking, buffer allocation.Steve Reinhardt
Single-cpu timing mode seems to work now. --HG-- extra : convert_revision : 720f6172df18a1c941e5bd0e8fdfbd686c13c7ad
2007-06-21Getting closer...Steve Reinhardt
configs/example/memtest.py: Add progress interval option. src/base/traceflags.py: Add MemTest flag. src/cpu/memtest/memtest.cc: Clean up tracing. src/cpu/memtest/memtest.hh: Get rid of unused code. --HG-- extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. --HG-- extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-05-22Fix getDeviceAddressRanges() to get snooping right.Steve Reinhardt
--HG-- extra : convert_revision : 2aeab25ef955ab9db7b968786faff227239fbbe4
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 src/mem/cache/base_cache.hh: Manual conflict resolution. --HG-- extra : convert_revision : 5ebfd7abb4f978caa88bf43d25935869edfc6b9f
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
--HG-- extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
Compiles but doesn't work... committing just so I can merge (stupid bk!). src/mem/bridge.cc: Get rid of SNOOP_COMMIT. src/mem/bus.cc: src/mem/packet.hh: Get rid of SNOOP_COMMIT & two-pass snoop. First bits of EXPRESS_SNOOP support. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/prefetch/base_prefetcher.cc: Big reorg of ports and port-related functions & events. src/mem/cache/cache.cc: src/mem/cache/cache_builder.cc: src/mem/cache/coherence/SConscript: Get rid of UniCoherence object. --HG-- extra : convert_revision : 7672434fa3115c9b1c94686f497e57e90413b7c3
2007-05-13Eliminate unused PacketPtr from BaseCache'sSteve Reinhardt
RequestEvent and ResponseEvent. Compiles but not tested. --HG-- extra : convert_revision : cc791e7adea5b0406e986a0076edba51856b9105
2007-05-13Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.Steve Reinhardt
Compiles but not tested. --HG-- extra : convert_revision : 4e1e28c4b87721ccfcf35a5ea62c1fa324acbaf9
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
Created MemCmd class to wrap enum and provide handy methods to check attributes, convert to string/int, etc. --HG-- extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-06Minor DPRINTF fixes.Steve Reinhardt
--HG-- extra : convert_revision : 41956c9a480163ecac7807982215027e8ff1a4a9
2006-12-13Split CachePort class into CpuSidePort and MemSidePortSteve Reinhardt
and push those into derived Cache template class to eliminate a few layers of virtual functions and conditionals ("if (isCpuSide) { ... }" etc.). --HG-- extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
2006-11-13Fix a bug to handle the fact that a CPU can send Functional accesses while a ↵Ron Dreslinski
sendTiming has not returned in the call stack. src/mem/cache/base_cache.cc: Sometimes a functional access comes while waiting on a outstanding packet being sent. This could be because Timing CPU does some post processing on the recvTiming which send functional access. Either the CPU should leave the pkt/req around (so They can be referenced in the mem system). Or the mem system should remove them from outstanding lists and reinsert them if they fail in the sendTiming. I did the later, eventually we should consider doing the former if that is the correct behavior. --HG-- extra : convert_revision : be41e0d2632369dca9d7c15e96e5576d7583fe6a
2006-11-12Fix functional access errors related to delayed respnoses in cachePortRon Dreslinski
src/mem/cache/base_cache.cc: On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag. src/mem/packet.cc: src/mem/packet.hh: Create a wrapper to toggle the hasData flag on delayed responses --HG-- extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
2006-11-10More fixes for functional accesses. It now makes the writeback memory leak ↵Ron Dreslinski
to crash all configs. Working on that now. src/mem/cache/base_cache.cc: Keep a list of the responders so we can search them on functional accesses. src/mem/cache/base_cache.hh: Properly put things on a list for responses so we can search the list. Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there) src/mem/cache/cache_impl.hh: Properly return when the first read hit on a functional access. Make sure to call to check the other ports list of packets before forwarding it out. --HG-- extra : convert_revision : 1d21cb55ff29c15716617efc48441329707c088a
2006-11-07Fix up bus draining and add draining to the caches.Kevin Lim
src/mem/bus.cc: Fix up draining to work properly. src/mem/bus.hh: Initialize drainEvent to NULL. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: Add draining to the caches. --HG-- extra : convert_revision : 3082220a75d50876f10909f9f99bec535889f818
2006-11-02Caches return a new functional port whenever asked for one.Kevin Lim
src/mem/cache/base_cache.cc: Have caches return a new functional port whenever asked for them. I'm pretty sure this is desired behavior. Ron can correct me if it's not. --HG-- extra : convert_revision : e1fadf895a7d714968128ff900d10e86fde53387
2006-10-31Ports now have a pointer to the MemObject that owns it (can be NULL).Kevin Lim
src/cpu/simple/atomic.hh: Port now takes in the MemObject that owns it. src/cpu/simple/timing.hh: Port now takes in MemObject that owns it. src/dev/io_device.cc: src/mem/bus.hh: Ports now take in the MemObject that owns it. src/mem/cache/base_cache.cc: Ports now take in the MemObject that own it. src/mem/port.hh: src/mem/tport.hh: Ports now optionally take in the MemObject that owns it. --HG-- extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
2006-10-22Clean up cache DPRINTFsSteve Reinhardt
--HG-- extra : convert_revision : f836e77efd40e25259d7794dd148696586b79a09
2006-10-20Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest src/mem/tport.cc: Merge PacketPtr changes --HG-- extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
2006-10-20Use fixPacket function everywhere.Ron Dreslinski
Fix fixPacket assert function. Stop timing port from forwarding the request if a response was found in its queue on a read. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/python/m5/objects/MemTest.py: Add parameter to configure what percentage of mem accesses are functional src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Use fix Packet function src/mem/packet.cc: Fix an assert that was checking the wrong thing src/mem/tport.cc: Properly detect if we need to do the access to the functional device --HG-- extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
2006-10-20Use PacketPtr everywhereNathan Binkert
--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
and call it packet_access.hh and fix the #includes so things compile right. --HG-- extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-19Fix corner case on assertion.Ron Dreslinski
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere. Still a functional access bug someplace I need to track down in timing mode. src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Fix corner case on assertion tests/configs/memtest.py: Updated memtester with uncacheable addresses and functional accesses --HG-- extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
2006-10-18Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
2006-10-17Include packet_impl.hh (need this on my laptop,Steve Reinhardt
but not on zizzer... g++ 4 thing maybe?) --HG-- extra : convert_revision : 31c49f1c55fe9daf6365411bfb5bb7f6ccc8032d
2006-10-17Fixes for uni-coherence in timing mode for FS.Ron Dreslinski
Still a bug in atomic uni-coherence in FS. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Make CPU models handle coherence requests src/mem/cache/base_cache.cc: Properly signal coherence CSHRs src/mem/cache/coherence/uni_coherence.cc: Only deallocate once --HG-- extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
2006-10-17Fixes to cache eliminating the assumption that the Packet is still valid ↵Ron Dreslinski
after sending out a request. Still need to rework upgrades into this system, but works for now. src/mem/cache/base_cache.cc: Re order code to be more readable src/mem/cache/base_cache.hh: Be sure to delete the copy on a bus block src/mem/cache/cache_impl.hh: Be sure to remove the copy on a writeback success src/mem/cache/miss/mshr_queue.cc: Demorgans to make it easier to understand src/mem/tport.cc: Delete writebacks --HG-- extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
2006-10-17Fix it so that the cache does not assume to gave the packet it sent out via ↵Ron Dreslinski
sendTiming. Still need to fix upgrades to use this path src/mem/cache/base_cache.cc: Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed src/mem/cache/cache_impl.hh: Use copy of packet, because sendTiming may have changed the pkt Also, delete the copy when the time comes --HG-- extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
2006-10-13Fix for DMA's in FS caches.Ron Dreslinski
Fix CSHR's for flow control. Fix for Bus Bridges reusing packets (clean flags up) Now both timing/atomic caches with MOESI in UP fail at same point. src/dev/io_device.hh: DMA's should send WriteInvalidates src/mem/bridge.cc: Reusing packet, clean flags in the packet set by bus. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Fix CSHR's for flow control. src/mem/packet.hh: Make a writeInvalidateResp, since the DMA expects responses to it's writes --HG-- extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
2006-10-12Fix CSHR retrysRon Dreslinski
--HG-- extra : convert_revision : caa7664f6c945396fa38ce62fbda018ebed4eaa6
2006-10-12Check the response queue on functional accesses.Ron Dreslinski
The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses? src/mem/cache/base_cache.cc: src/mem/tport.cc: Add in functional check of retry queued packets. --HG-- extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
2006-10-11Use bus response time paramteresRon Dreslinski
Fix bug with deadlocking src/mem/cache/base_cache.cc: Make sure to not wait anymore --HG-- extra : convert_revision : 5f7b44a1c475820b9862275a0d6113ec2991735d
2006-10-11When turning asserts into if's don't forget to invert.Ron Dreslinski
src/mem/cache/base_cache.cc: When turning asserts into if's don't forget to invert. Must be too sleepy. --HG-- extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
2006-10-11Writebacks can be pulled out from under the BusRequest when snoops of ↵Ron Dreslinski
uprgades to owned blocks hit in the WB buffer --HG-- extra : convert_revision : f0502836a79ce303150daa7e571badb0bce3a97a
2006-10-10Only issue responses if we aren;t already blockedRon Dreslinski
--HG-- extra : convert_revision : 511c0bcd44b93d5499eefa8399f36ef8b6607311
2006-10-10Debugging infoRon Dreslinski
src/base/traceflags.py: Add new flags for cacheport src/mem/bus.cc: Add debugging info src/mem/cache/base_cache.cc: Add debuggin info --HG-- extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
2006-10-10Some more code cleanupRon Dreslinski
src/mem/cache/base_cache.cc: Add sanity checks src/mem/cache/base_cache.hh: Fix for retry mechanism --HG-- extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
2006-10-10Fix some more mem leaks, still some leftRon Dreslinski
Update retry mechanism src/mem/cache/base_cache.cc: Rework the retry mechanism src/mem/cache/base_cache.hh: Rework the retry mechanism Try to fix memory bug src/mem/cache/cache_impl.hh: Rework upgrades to not be blocked by slave src/mem/cache/miss/mshr_queue.cc: Fix mem leak on writebacks --HG-- extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
2006-10-10Fix cshr Retry'sRon Dreslinski
Fix Upgrades being blocked by slave --HG-- extra : convert_revision : cca98a38e32233145163577500f1362cd807ab15
2006-10-10Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest src/mem/packet.hh: Hand merge code --HG-- extra : convert_revision : d659418f24f4f4bf9867fec8573a5d227c0dfcea
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 14:50:46 +0000