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path: root/src/mem/cache/base_cache.cc
AgeCommit message (Expand)Author
2006-12-13Split CachePort class into CpuSidePort and MemSidePortSteve Reinhardt
2006-11-13Fix a bug to handle the fact that a CPU can send Functional accesses while a ...Ron Dreslinski
2006-11-12Fix functional access errors related to delayed respnoses in cachePortRon Dreslinski
2006-11-10More fixes for functional accesses. It now makes the writeback memory leak t...Ron Dreslinski
2006-11-07Fix up bus draining and add draining to the caches.Kevin Lim
2006-11-02Caches return a new functional port whenever asked for one.Kevin Lim
2006-10-31Ports now have a pointer to the MemObject that owns it (can be NULL).Kevin Lim
2006-10-22Clean up cache DPRINTFsSteve Reinhardt
2006-10-20Merge zizzer:/bk/newmemRon Dreslinski
2006-10-20Use fixPacket function everywhere.Ron Dreslinski
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
2006-10-19Fix corner case on assertion.Ron Dreslinski
2006-10-18Merge zizzer:/bk/newmemRon Dreslinski
2006-10-17Include packet_impl.hh (need this on my laptop,Steve Reinhardt
2006-10-17Fixes for uni-coherence in timing mode for FS.Ron Dreslinski
2006-10-17Fixes to cache eliminating the assumption that the Packet is still valid afte...Ron Dreslinski
2006-10-17Fix it so that the cache does not assume to gave the packet it sent out via s...Ron Dreslinski
2006-10-13Fix for DMA's in FS caches.Ron Dreslinski
2006-10-12Fix CSHR retrysRon Dreslinski
2006-10-12Check the response queue on functional accesses.Ron Dreslinski
2006-10-11Use bus response time paramteresRon Dreslinski
2006-10-11When turning asserts into if's don't forget to invert.Ron Dreslinski
2006-10-11Writebacks can be pulled out from under the BusRequest when snoops of uprgade...Ron Dreslinski
2006-10-10Only issue responses if we aren;t already blockedRon Dreslinski
2006-10-10Debugging infoRon Dreslinski
2006-10-10Some more code cleanupRon Dreslinski
2006-10-10Fix some more mem leaks, still some leftRon Dreslinski
2006-10-10Fix cshr Retry'sRon Dreslinski
2006-10-10Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-10-10Fix several bugs pertaining to upgrades/mem leaks.Ron Dreslinski
2006-10-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-09One step closet to having NACK's work.Ron Dreslinski
2006-10-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-09Set size properly on uncache accessesRon Dreslinski
2006-10-09Don't block responses even if the cache is blocked.Ron Dreslinski
2006-10-08missing elseGabe Black
2006-10-07Fix a missing pointerRon Dreslinski
2006-10-07No need to keep trying to request the data bus if we are already waiting.Ron Dreslinski
2006-10-07Add mechanism for caches to handle failure of the fast path on responses.Ron Dreslinski
2006-10-05First pass at snooping stuff that compiles and doesn't break.Ron Dreslinski
2006-08-17Changes to build m5.fastSteve Reinhardt
2006-08-16Fixes for blocking in the caches that needed to be pulledRon Dreslinski
2006-08-15Some changes to support blocking in the cachesRon Dreslinski
2006-07-10Some fixes so that MSHR's are matched and we don't issue overlapping requests...Ron Dreslinski
2006-07-07Fix address range calculation. Still need bus to handle snoop ranges.Ron Dreslinski
2006-07-07Update cpus to use the getPort function to use a connector object to connect ...Ron Dreslinski
2006-07-06Timing cache works for hello world test.Ron Dreslinski
2006-07-06Now timing reads work in single level of cache with simple cpuRon Dreslinski
2006-06-30First pass, now compiles with current head of tree.Ron Dreslinski
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