index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mem
/
cache
/
base_cache.cc
Age
Commit message (
Expand
)
Author
2007-02-07
Make memory commands dense again to avoid cache stat table explosion.
Steve Reinhardt
2007-02-06
Minor DPRINTF fixes.
Steve Reinhardt
2006-12-13
Split CachePort class into CpuSidePort and MemSidePort
Steve Reinhardt
2006-11-13
Fix a bug to handle the fact that a CPU can send Functional accesses while a ...
Ron Dreslinski
2006-11-12
Fix functional access errors related to delayed respnoses in cachePort
Ron Dreslinski
2006-11-10
More fixes for functional accesses. It now makes the writeback memory leak t...
Ron Dreslinski
2006-11-07
Fix up bus draining and add draining to the caches.
Kevin Lim
2006-11-02
Caches return a new functional port whenever asked for one.
Kevin Lim
2006-10-31
Ports now have a pointer to the MemObject that owns it (can be NULL).
Kevin Lim
2006-10-22
Clean up cache DPRINTFs
Steve Reinhardt
2006-10-20
Merge zizzer:/bk/newmem
Ron Dreslinski
2006-10-20
Use fixPacket function everywhere.
Ron Dreslinski
2006-10-20
Use PacketPtr everywhere
Nathan Binkert
2006-10-19
refactor code for the packet, get rid of packet_impl.hh
Nathan Binkert
2006-10-19
Fix corner case on assertion.
Ron Dreslinski
2006-10-18
Merge zizzer:/bk/newmem
Ron Dreslinski
2006-10-17
Include packet_impl.hh (need this on my laptop,
Steve Reinhardt
2006-10-17
Fixes for uni-coherence in timing mode for FS.
Ron Dreslinski
2006-10-17
Fixes to cache eliminating the assumption that the Packet is still valid afte...
Ron Dreslinski
2006-10-17
Fix it so that the cache does not assume to gave the packet it sent out via s...
Ron Dreslinski
2006-10-13
Fix for DMA's in FS caches.
Ron Dreslinski
2006-10-12
Fix CSHR retrys
Ron Dreslinski
2006-10-12
Check the response queue on functional accesses.
Ron Dreslinski
2006-10-11
Use bus response time paramteres
Ron Dreslinski
2006-10-11
When turning asserts into if's don't forget to invert.
Ron Dreslinski
2006-10-11
Writebacks can be pulled out from under the BusRequest when snoops of uprgade...
Ron Dreslinski
2006-10-10
Only issue responses if we aren;t already blocked
Ron Dreslinski
2006-10-10
Debugging info
Ron Dreslinski
2006-10-10
Some more code cleanup
Ron Dreslinski
2006-10-10
Fix some more mem leaks, still some left
Ron Dreslinski
2006-10-10
Fix cshr Retry's
Ron Dreslinski
2006-10-10
Merge zizzer:/z/m5/Bitkeeper/newmem
Ron Dreslinski
2006-10-10
Fix several bugs pertaining to upgrades/mem leaks.
Ron Dreslinski
2006-10-09
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2006-10-09
One step closet to having NACK's work.
Ron Dreslinski
2006-10-09
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2006-10-09
Set size properly on uncache accesses
Ron Dreslinski
2006-10-09
Don't block responses even if the cache is blocked.
Ron Dreslinski
2006-10-08
missing else
Gabe Black
2006-10-07
Fix a missing pointer
Ron Dreslinski
2006-10-07
No need to keep trying to request the data bus if we are already waiting.
Ron Dreslinski
2006-10-07
Add mechanism for caches to handle failure of the fast path on responses.
Ron Dreslinski
2006-10-05
First pass at snooping stuff that compiles and doesn't break.
Ron Dreslinski
2006-08-17
Changes to build m5.fast
Steve Reinhardt
2006-08-16
Fixes for blocking in the caches that needed to be pulled
Ron Dreslinski
2006-08-15
Some changes to support blocking in the caches
Ron Dreslinski
2006-07-10
Some fixes so that MSHR's are matched and we don't issue overlapping requests...
Ron Dreslinski
2006-07-07
Fix address range calculation. Still need bus to handle snoop ranges.
Ron Dreslinski
2006-07-07
Update cpus to use the getPort function to use a connector object to connect ...
Ron Dreslinski
2006-07-06
Timing cache works for hello world test.
Ron Dreslinski
[next]