gem5 - gem5

Age	Commit message (Expand)	Author
2014-12-02	mem: Remove WriteInvalidate support	Curtis Dunham
2014-06-27	mem: write streaming support via WriteInvalidate promotion	Curtis Dunham
2014-05-13	cpu, mem: Make software prefetches non-blocking	Curtis Dunham
2014-04-01	mem: Don't print out the data of a cache block	Mitch Hayenga
2014-01-24	mem: Add support for a security bit in the memory system	Giacomo Gabrielli
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2013-04-22	mem: Adding verbose debug output in the memory system	Uri Wiener
2013-01-08	mem: Make LL/SC locks fine grained	Mitch Hayenga
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg
2012-09-11	Cache: Split invalidateBlk up to seperate block vs. tags	Lena Olson
2012-02-12	mem: fix cache stats to use request ids correctly	Dam Sunwoo
2011-04-15	includes: sort all includes	Nathan Binkert
2011-02-23	Includes: Don't include isa_traits.hh and use the TheISA namespace unless rea...	Ali Saidi
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-02-23	cache: Make caches sharing aware and add occupancy stats.	Lisa Hsu
2010-02-23	cache: pull CacheSet out of LRU so that other tags can use associative sets.	Lisa Hsu
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2009-04-19	Mem: Change isLlsc to isLLSC.	Gabe Black
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black
2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-09-10	style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...	Ali Saidi
2008-02-26	Revamp cache timing access mshr check to make stats sane again.	Steve Reinhardt
2008-02-10	Rename cache files for brevity and consistency with rest of tree.	Steve Reinhardt