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path: root/src/mem/cache/cache.hh
AgeCommit message (Expand)Author
2014-01-28mem: Remove redundant findVictim() input argumentAmin Farmahini
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-07-18mem: Add cache class destructor to avoid memory leaksXiangyu Dong
2013-06-27mem: Reorganize cache tags and make them a SimObjectPrakash Ramrakhyani
2013-06-27mem: Cycles converted to Ticks in atomic cache accessesAndreas Hansson
2013-02-19mem: Change accessor function names to match the port interfaceAndreas Hansson
2013-02-15mem: Tighten up cache constness and scopingAndreas Hansson
2013-01-07mem: Fix guest corruption when caches handle uncacheable accessesAndreas Sandberg
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25MEM: Put memory system document into doxygenDjordje Kovacevic
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-06-07mem: Delay deleting of incoming packets by one call.Ali Saidi
2012-05-24Cache: Remove dangling doWriteback declarationAndreas Hansson
2012-05-10Cache: Panic if you attempt to create a checkpoint with a cache in the systemAli Saidi
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
2012-01-17MEM: Differentiate functional cache accesses from CPU and memoryAndreas Hansson
2011-04-15includes: sort all includesNathan Binkert
2010-09-09cache: coherence protocol enhancements & bug fixesSteve Reinhardt
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
2009-02-16Fixes to get prefetching working again.Steve Reinhardt
2008-10-23s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos inLisa Hsu
2008-10-23probe function no longer used anywhere.Lisa Hsu
2008-10-14This function declaration isn't used anywhere.Lisa Hsu
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
2008-03-25Fix handling of writeback-induced writebacks in atomic mode.Steve Reinhardt
2008-02-26Cache: better comments particularly regarding writeback situation.Steve Reinhardt
2008-02-16Make L2+ caches allocate new block for writeback missesSteve Reinhardt
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-07-22Replace lowerMSHRPending flag with more robust schemeSteve Reinhardt
2007-07-22Replace DeferredSnoop flag with LowerMSHRPending flag.Steve Reinhardt
2007-06-27Get rid of coherence protocol object.Steve Reinhardt
2007-06-26Revamp replacement-of-upgrade handling.Steve Reinhardt
2007-06-26Handle deferred snoops better.Steve Reinhardt
2007-06-24Better handling of deferred targets.Steve Reinhardt
2007-06-22Fixes to hitLatency, blocking, buffer allocation.Steve Reinhardt
2007-06-21Getting closer...Steve Reinhardt
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