gem5 - gem5

Age	Commit message (Expand)	Author
2016-08-12	mem: Update mostly exclusive cache policy to cover more cases	Andreas Hansson
2016-05-26	mem: change NULL to nullptr in the cache related classes	Nikos Nikoleris
2016-04-21	mem: Align downstream cache packet creation in atomic and timing	Andreas Hansson
2016-03-17	mem: Create a separate class for the cache write buffer	Andreas Hansson
2015-12-31	mem: Make cache terminology easier to understand	Andreas Hansson
2015-12-28	mem: Do not use sender state to track forwarded snoops in cache	Andreas Hansson
2015-11-15	arm: Add missing explicit overrides for classic caches	Andreas Sandberg
2015-11-06	mem: Add an option to perform clean writebacks from caches	Andreas Hansson
2015-11-06	mem: Add cache clusivity	Andreas Hansson
2015-11-06	mem: Unify delayed packet deletion	Andreas Hansson
2015-10-12	misc: Add explicit overrides and fix other clang >= 3.5 issues	Andreas Hansson
2015-10-12	misc: Remove redundant compiler-specific defines	Andreas Hansson
2015-09-25	mem: Add snoops for CleanEvicts and Writebacks in atomic mode	Ali Jafri
2015-09-25	mem: Make the coherent crossbar account for timing snoops	Andreas Hansson
2015-08-21	mem: Remove unused cache squash functionality	Andreas Hansson
2015-08-21	mem: Add explicit Cache subclass and make BaseCache abstract	Andreas Hansson
2015-08-21	mem: Move cache_impl.hh to cache.cc	Andreas Hansson
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-07-03	mem: Add clean evicts to improve snoop filter tracking	Ali Jafri
2015-05-05	mem: Remove templates in cache model	David Guillen
2015-03-27	mem: Allocate cache writebacks before new MSHRs	Andreas Hansson
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-02-03	mem: Clarify cache behaviour for pending dirty responses	Andreas Hansson
2014-12-02	mem: Add const getters for write packet data	Andreas Hansson
2014-10-09	mem: Add packet sanity checks to cache and MSHRs	Andreas Hansson
2014-06-27	mem: write streaming support via WriteInvalidate promotion	Curtis Dunham
2014-05-13	cpu, mem: Make software prefetches non-blocking	Curtis Dunham
2014-01-28	mem: Remove redundant findVictim() input argument	Amin Farmahini
2014-01-24	mem: Add support for a security bit in the memory system	Giacomo Gabrielli
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-07-18	mem: Add cache class destructor to avoid memory leaks	Xiangyu Dong
2013-06-27	mem: Reorganize cache tags and make them a SimObject	Prakash Ramrakhyani
2013-06-27	mem: Cycles converted to Ticks in atomic cache accesses	Andreas Hansson
2013-02-19	mem: Change accessor function names to match the port interface	Andreas Hansson
2013-02-15	mem: Tighten up cache constness and scoping	Andreas Hansson
2013-01-07	mem: Fix guest corruption when caches handle uncacheable accesses	Andreas Sandberg
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-09-25	MEM: Put memory system document into doxygen	Djordje Kovacevic
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-06-07	mem: Delay deleting of incoming packets by one call.	Ali Saidi
2012-05-24	Cache: Remove dangling doWriteback declaration	Andreas Hansson
2012-05-10	Cache: Panic if you attempt to create a checkpoint with a cache in the system	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-02-24	MEM: Simplify cache ports preparing for master/slave split	Andreas Hansson
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson