gem5 - gem5

Age	Commit message (Expand)	Author
2012-05-24	Cache: Remove dangling doWriteback declaration	Andreas Hansson
2012-05-10	Cache: Panic if you attempt to create a checkpoint with a cache in the system	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-02-24	MEM: Simplify cache ports preparing for master/slave split	Andreas Hansson
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Remove Port removeConn and MemObject deletePortRefs	Andreas Hansson
2012-01-17	MEM: Differentiate functional cache accesses from CPU and memory	Andreas Hansson
2011-04-15	includes: sort all includes	Nathan Binkert
2010-09-09	cache: coherence protocol enhancements & bug fixes	Steve Reinhardt
2008-07-16	mem: use single BadAddr responder per system.	Steve Reinhardt
2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
2008-10-23	s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in	Lisa Hsu
2008-10-23	probe function no longer used anywhere.	Lisa Hsu
2008-10-14	This function declaration isn't used anywhere.	Lisa Hsu
2008-06-28	Backed out changeset 94a7bb476fca: caused memory leak.	Steve Reinhardt
2008-06-21	Generate more useful error messages for unconnected ports.	Steve Reinhardt
2008-03-25	Fix handling of writeback-induced writebacks in atomic mode.	Steve Reinhardt
2008-02-26	Cache: better comments particularly regarding writeback situation.	Steve Reinhardt
2008-02-16	Make L2+ caches allocate new block for writeback misses	Steve Reinhardt
2008-02-10	Fix #include lines for renamed cache files.	Steve Reinhardt
2008-01-02	Add ReadRespWithInvalidate to handle multi-level coherence situation	Steve Reinhardt
2008-01-02	Add functional PrintReq command for memory-system debugging.	Steve Reinhardt
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-07-22	Replace lowerMSHRPending flag with more robust scheme	Steve Reinhardt
2007-07-22	Replace DeferredSnoop flag with LowerMSHRPending flag.	Steve Reinhardt
2007-06-27	Get rid of coherence protocol object.	Steve Reinhardt
2007-06-26	Revamp replacement-of-upgrade handling.	Steve Reinhardt
2007-06-26	Handle deferred snoops better.	Steve Reinhardt
2007-06-24	Better handling of deferred targets.	Steve Reinhardt
2007-06-22	Fixes to hitLatency, blocking, buffer allocation.	Steve Reinhardt
2007-06-21	Getting closer...	Steve Reinhardt
2007-06-17	More major reorg of cache. Seems to work for atomic mode now,	Steve Reinhardt
2007-05-22	Fix getDeviceAddressRanges() to get snooping right.	Steve Reinhardt
2007-05-18	First set of changes for reorganized cache coherence support.	Steve Reinhardt
2007-03-27	First Pass At Cmp/Swap in caches	Ron Dreslinski
2007-03-08	stop m5 from leaking like a sieve	Ali Saidi
2006-12-18	Streamline Cache/Tags interface: get rid of redundant functions,	Steve Reinhardt
2006-12-18	No need to template prefetcher on cache TagStore type.	Steve Reinhardt
2006-12-18	Get rid of generic CacheTags object (fold back into Cache).	Steve Reinhardt
2006-12-13	Split CachePort class into CpuSidePort and MemSidePort	Steve Reinhardt
2006-12-04	Turn cache MissQueue/BlockingBuffer into virtual object	Steve Reinhardt
2006-10-20	Use PacketPtr everywhere	Nathan Binkert
2006-10-18	Get rid of obsolete in-cache copy support.	Steve Reinhardt
2006-10-13	Fix for DMA's in FS caches.	Ron Dreslinski
2006-10-10	Fix several bugs pertaining to upgrades/mem leaks.	Ron Dreslinski