index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mem
/
cache
/
cache.hh
Age
Commit message (
Expand
)
Author
2008-01-02
Add ReadRespWithInvalidate to handle multi-level coherence situation
Steve Reinhardt
2008-01-02
Add functional PrintReq command for memory-system debugging.
Steve Reinhardt
2007-08-30
params: Deprecate old-style constructors; update most SimObject constructors.
Miles Kaufmann
2007-08-10
DMA: Add IOCache and fix bus bridge to optionally only send requests one
Ali Saidi
2007-07-22
Replace lowerMSHRPending flag with more robust scheme
Steve Reinhardt
2007-07-22
Replace DeferredSnoop flag with LowerMSHRPending flag.
Steve Reinhardt
2007-06-27
Get rid of coherence protocol object.
Steve Reinhardt
2007-06-26
Revamp replacement-of-upgrade handling.
Steve Reinhardt
2007-06-26
Handle deferred snoops better.
Steve Reinhardt
2007-06-24
Better handling of deferred targets.
Steve Reinhardt
2007-06-22
Fixes to hitLatency, blocking, buffer allocation.
Steve Reinhardt
2007-06-21
Getting closer...
Steve Reinhardt
2007-06-17
More major reorg of cache. Seems to work for atomic mode now,
Steve Reinhardt
2007-05-22
Fix getDeviceAddressRanges() to get snooping right.
Steve Reinhardt
2007-05-18
First set of changes for reorganized cache coherence support.
Steve Reinhardt
2007-03-27
First Pass At Cmp/Swap in caches
Ron Dreslinski
2007-03-08
stop m5 from leaking like a sieve
Ali Saidi
2006-12-18
Streamline Cache/Tags interface: get rid of redundant functions,
Steve Reinhardt
2006-12-18
No need to template prefetcher on cache TagStore type.
Steve Reinhardt
2006-12-18
Get rid of generic CacheTags object (fold back into Cache).
Steve Reinhardt
2006-12-13
Split CachePort class into CpuSidePort and MemSidePort
Steve Reinhardt
2006-12-04
Turn cache MissQueue/BlockingBuffer into virtual object
Steve Reinhardt
2006-10-20
Use PacketPtr everywhere
Nathan Binkert
2006-10-18
Get rid of obsolete in-cache copy support.
Steve Reinhardt
2006-10-13
Fix for DMA's in FS caches.
Ron Dreslinski
2006-10-10
Fix several bugs pertaining to upgrades/mem leaks.
Ron Dreslinski
2006-10-09
Set size properly on uncache accesses
Ron Dreslinski
2006-10-05
Fixes for functional accesses to use the snoop path.
Ron Dreslinski
2006-08-15
Pulled out changes to fix EIO programs with caches. Also fixes any translati...
Ron Dreslinski
2006-08-14
Fix up doxygen.
Steve Reinhardt
2006-07-06
Timing cache works for hello world test.
Ron Dreslinski
2006-07-06
Now timing reads work in single level of cache with simple cpu
Ron Dreslinski
2006-06-30
First pass, now compiles with current head of tree.
Ron Dreslinski
2006-06-30
Fix the packet data allocation methods. Small fixes from changesets after my...
Ron Dreslinski
2006-06-29
Still missing prefetch and tags directories as well as cache builder.
Ron Dreslinski
2006-06-28
More Changes, working towards cache.cc compiling. Headers cleaned up.
Ron Dreslinski
2006-06-28
Backing in more changsets, getting closer to compile
Ron Dreslinski
2006-06-28
Was having difficulty with merging the cache, reverted to an early version an...
Ron Dreslinski