gem5 - gem5

Age	Commit message (Expand)	Author
2015-05-05	mem: Remove templates in cache model	David Guillen
2015-03-27	mem: Allocate cache writebacks before new MSHRs	Andreas Hansson
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-02-03	mem: Clarify cache behaviour for pending dirty responses	Andreas Hansson
2014-12-02	mem: Add const getters for write packet data	Andreas Hansson
2014-10-09	mem: Add packet sanity checks to cache and MSHRs	Andreas Hansson
2014-06-27	mem: write streaming support via WriteInvalidate promotion	Curtis Dunham
2014-05-13	cpu, mem: Make software prefetches non-blocking	Curtis Dunham
2014-01-28	mem: Remove redundant findVictim() input argument	Amin Farmahini
2014-01-24	mem: Add support for a security bit in the memory system	Giacomo Gabrielli
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-07-18	mem: Add cache class destructor to avoid memory leaks	Xiangyu Dong
2013-06-27	mem: Reorganize cache tags and make them a SimObject	Prakash Ramrakhyani
2013-06-27	mem: Cycles converted to Ticks in atomic cache accesses	Andreas Hansson
2013-02-19	mem: Change accessor function names to match the port interface	Andreas Hansson
2013-02-15	mem: Tighten up cache constness and scoping	Andreas Hansson
2013-01-07	mem: Fix guest corruption when caches handle uncacheable accesses	Andreas Sandberg
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-09-25	MEM: Put memory system document into doxygen	Djordje Kovacevic
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-06-07	mem: Delay deleting of incoming packets by one call.	Ali Saidi
2012-05-24	Cache: Remove dangling doWriteback declaration	Andreas Hansson
2012-05-10	Cache: Panic if you attempt to create a checkpoint with a cache in the system	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-02-24	MEM: Simplify cache ports preparing for master/slave split	Andreas Hansson
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Remove Port removeConn and MemObject deletePortRefs	Andreas Hansson
2012-01-17	MEM: Differentiate functional cache accesses from CPU and memory	Andreas Hansson
2011-04-15	includes: sort all includes	Nathan Binkert
2010-09-09	cache: coherence protocol enhancements & bug fixes	Steve Reinhardt
2008-07-16	mem: use single BadAddr responder per system.	Steve Reinhardt
2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
2008-10-23	s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in	Lisa Hsu
2008-10-23	probe function no longer used anywhere.	Lisa Hsu
2008-10-14	This function declaration isn't used anywhere.	Lisa Hsu
2008-06-28	Backed out changeset 94a7bb476fca: caused memory leak.	Steve Reinhardt
2008-06-21	Generate more useful error messages for unconnected ports.	Steve Reinhardt
2008-03-25	Fix handling of writeback-induced writebacks in atomic mode.	Steve Reinhardt
2008-02-26	Cache: better comments particularly regarding writeback situation.	Steve Reinhardt
2008-02-16	Make L2+ caches allocate new block for writeback misses	Steve Reinhardt
2008-02-10	Fix #include lines for renamed cache files.	Steve Reinhardt
2008-01-02	Add ReadRespWithInvalidate to handle multi-level coherence situation	Steve Reinhardt
2008-01-02	Add functional PrintReq command for memory-system debugging.	Steve Reinhardt
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi