gem5 - gem5

Age	Commit message (Expand)	Author
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-06-27	Get rid of coherence protocol object.	Steve Reinhardt
2007-06-17	More major reorg of cache. Seems to work for atomic mode now,	Steve Reinhardt
2007-05-18	First set of changes for reorganized cache coherence support.	Steve Reinhardt
2007-05-10	remove hit_latency and make latency do the right thing	Ali Saidi
2006-12-18	No need to template prefetcher on cache TagStore type.	Steve Reinhardt
2006-12-18	Get rid of generic CacheTags object (fold back into Cache).	Steve Reinhardt
2006-12-05	Don't compress data on writebacks unless it's actually necessary.	Steve Reinhardt
2006-12-04	Turn cache MissQueue/BlockingBuffer into virtual object	Steve Reinhardt
2006-12-02	Make cache compression policy a runtime virtual thing	Steve Reinhardt
2006-10-18	Get rid of obsolete in-cache copy support.	Steve Reinhardt
2006-06-30	Fix the packet data allocation methods. Small fixes from changesets after my...	Ron Dreslinski
2006-06-29	Still missing prefetch and tags directories as well as cache builder.	Ron Dreslinski
2006-06-28	Was having difficulty with merging the cache, reverted to an early version an...	Ron Dreslinski