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cache_impl.hh
Age
Commit message (
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Author
2012-06-05
sim: Remove FastAlloc
Ali Saidi
2012-05-30
Bus: Turn the PortId into a transport function parameter
Andreas Hansson
2012-05-30
Packet: Unify the use of PortID in packet and port
Andreas Hansson
2012-05-10
Cache: restructure code that actually isn't a loop
Ali Saidi
2012-05-10
Cache: Panic if you attempt to create a checkpoint with a cache in the system
Ali Saidi
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-14
MEM: Remove the Broadcast destination from the packet
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-03-30
MEM: Introduce the master/slave port sub-classes in C++
William Wang
2012-03-22
MEM: Split SimpleTimingPort into PacketQueue and ports
Andreas Hansson
2012-03-09
cache: Allow main memory to be at disjoint address ranges.
Ali Saidi
2012-03-01
Cache: Fix an issue with LRU when bonus block is used to complete transaction.
Ali Saidi
2012-02-24
MEM: Simplify cache ports preparing for master/slave split
Andreas Hansson
2012-02-12
mem: fix cache stats to use request ids correctly
Dam Sunwoo
2012-02-12
mem: Add a master ID to each request object.
Ali Saidi
2012-02-12
prefetcher: Make prefetcher a sim object instead of it being a parameter on c...
Mrinmoy Ghosh
2012-01-31
MEM: Remove the otherPort from the cache ports
Andreas Hansson
2012-01-17
MEM: Remove the functional ports from the memory system
William Wang
2012-01-17
MEM: Separate queries for snooping and address ranges
Andreas Hansson
2012-01-17
MEM: Remove Port removeConn and MemObject deletePortRefs
Andreas Hansson
2012-01-17
MEM: Simplify ports by removing EventManager
Andreas Hansson
2012-01-17
MEM: Differentiate functional cache accesses from CPU and memory
Andreas Hansson
2011-09-13
Prefetch: Don't prefetch if address is in the write queue.
Ali Saidi
2011-08-19
Mem: Put prefetcher notify call before packet is deleted.
Ali Saidi
2011-08-19
Prefetcher: Fix some memory leaks with the prefetcher.
Ali Saidi
2011-07-15
Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
Ali Saidi
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2011-04-15
includes: sort all includes
Nathan Binkert
2011-03-17
Mem: Fix issue with dirty block being lost when entire block transferred to n...
Ali Saidi
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2010-10-18
cache: minor SC assertion fix
Steve Reinhardt
2010-10-13
Mem: Change the CLREX flag to CLEAR_LL.
Gabe Black
2010-09-21
cache: improve coherence handling of writebacks
Steve Reinhardt
2010-09-09
cache: fail SC when invalidated while waiting for bus
Steve Reinhardt
2010-09-09
mem: fix functional accesses to deal with coherence change
Steve Reinhardt
2010-09-09
cache: coherence protocol enhancements & bug fixes
Steve Reinhardt
2010-08-26
mem: fix m5.fast compile bug in previous cset
Steve Reinhardt
2010-08-25
cache: fix a bug in atomic multilevel snoops
Steve Reinhardt
2010-08-23
MEM: Make CLREX a first class request operation and clear locks in caches whe...
Gene Wu
2010-08-23
ARM: Make sure that software prefetch instructions can't change the state of ...
Gene Wu
2010-07-22
Port: Only indicate that a SimpleTimingPort is drained if its send event is
Timothy M. Jones
2010-07-08
cache: fix bug in SC upgrade handling
Steve Reinhardt
2010-06-22
cache: fix longstanding prefetcher bug
Steve Reinhardt
2010-06-16
cache: fail store conditionals when upgrade loses race
Steve Reinhardt
2010-06-16
cache: fix dirty bit setting
Steve Reinhardt
2010-02-23
cache: Make caches sharing aware and add occupancy stats.
Lisa Hsu
2010-01-12
cache: make tags->insertBlock() and tags->accessBlock() context aware so that...
Lisa Hsu
2009-09-26
Minor cleanup: Use the blockAlign() method where it applies in the cache.
Steve Reinhardt
2009-09-26
Force prefetches to check cache and MSHRs immediately prior to issue.
Steve Reinhardt
2009-08-01
Fix setting of INST_FETCH flag for O3 CPU.
Steve Reinhardt
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