| Age | Commit message (Collapse) | Author |
|---|
|
|
|
|
|
when it in received
|
|
the TLB
|
|
not scheduled, as well as the transmit list being empty.
|
|
This bug was introduced with the recent rework of SC
failure handling in cset f97b62be544f.
|
|
Thanks to Joe Gross for pointing this out (again?).
Apologies to anyone who pointed it out earlier and
we didn't listen.
|
|
Requires new "SCUpgradeReq" message that marks upgrades
for store conditionals, so downstream caches can fail
these when they run into invalidations.
See http://www.m5sim.org/flyspray/task/197
|
|
Only set the dirty bit when we actually write to a block
(not if we thought we might but didn't, as in a failed
SC or CAS). This requires makeing sure the dirty bit
stays set when we get an exclusive (writable) copy
in a cache-to-cache transfer from another owner, which
n turn requires copying the mem-inhibit flag from
timing-mode requests to their associated responses.
|
|
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).
|
|
that the cache can make context-specific decisions within their various tag policy implementations.
|
|
|
|
This prevents redundant prefetches from being issued, solving the
occasional 'needsExclusive && !blk->isWritable()' assertion failure
in cache_impl.hh that several people have run into.
Eliminates "prefetch_cache_check_push" flag, neither setting of
which really solved the problem.
|
|
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
|
|
|
|
--HG--
rename : src/sim/host.hh => src/base/types.hh
|
|
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
|
|
|
|
|
|
|
|
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
|
|
Makes adding write-through operations easier.
|
|
|
|
connotations for what is really happening and how it should be used.
|
|
redundancies with threadId() as their replacement.
|
|
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
|
|
|
|
Force all non-default ports to provide a name and an
owner in the constructor.
|
|
I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.
|
|
--HG--
extra : convert_revision : 4fa64f8a929f1aa36a9d5a71b8d1816b497aca4c
|
|
--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
|
|
getting wrong writeback address.
--HG--
extra : convert_revision : 023dfb69c227c13a69bfe2744c6af75a45828b0b
|
|
--HG--
extra : convert_revision : 00db19f0698c0786f0dff561eea9217860a5a05a
|
|
if a prior write miss arrived while an even earlier
read miss was still outstanding.
--HG--
extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a
|
|
--HG--
extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
|
|
--HG--
extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
|
|
instead of forwarding down the line.
--HG--
extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
|
|
--HG--
extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
|
|
http://www.m5sim.org/flyspray/task/197
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>
--HG--
extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81
|
|
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us. We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A. This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.
--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
|
|
--HG--
extra : convert_revision : 6358c014d14a19a34111c39827b05987507544bb
|
|
--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
|
|
--HG--
extra : convert_revision : 26d71cca5420ad03e16bf174e15dabe7f902da41
|
|
--HG--
extra : convert_revision : c04281bcfc4cd23c7613aeccb21dc74452bcc951
|
|
Not so much noise on failed sends, and more complete
info when grepping a trace using an address.
--HG--
extra : convert_revision : 05a8261c9452072ca08b906200c6322b33e2b9f1
|
|
SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
|
|
--HG--
extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
|
|
--HG--
extra : convert_revision : 31aad7170b35556a4c984f4ebc013137d55d85eb
|
|
way so a cache can handle partial block requests for i/o devices.
--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
|
|
Make sure not to keep processing functional accesses
after they've been responded to.
Also use checkFunctional() return value instead of checking
packet command field where possible, mostly just for consistency.
--HG--
extra : convert_revision : 29fc76bc18731bd93a4ed05a281297827028ef75
|
