| Age | Commit message (Expand) | Author |
|---|
| 2014-03-07 | mem: Fix incorrect assert failure in the Cache | Prakash Ramrakhyani |
| 2014-02-18 | mem: Filter cache snoops based on address ranges | Andreas Hansson |
| 2014-01-29 | mem: prefetcher: add options, support for unaligned addresses | Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E) |
| 2014-01-28 | mem: Remove redundant findVictim() input argument | Amin Farmahini |
| 2014-01-24 | mem: Add support for a security bit in the memory system | Giacomo Gabrielli |
| 2014-01-24 | mem: per-thread cache occupancy and per-block ages | Dam Sunwoo |
| 2013-10-17 | cpu: add consistent guarding to *_impl.hh files. | Matt Horsnell |
| 2013-07-18 | mem: Add cache class destructor to avoid memory leaks | Xiangyu Dong |
| 2013-06-27 | mem: Reorganize cache tags and make them a SimObject | Prakash Ramrakhyani |
| 2013-06-27 | mem: Align cache timing to clock edges | Andreas Hansson |
| 2013-06-27 | mem: Cycles converted to Ticks in atomic cache accesses | Andreas Hansson |
| 2013-06-27 | mem: Remove a redundant heap allocation for a snoop packet | Andreas Hansson |
| 2013-04-22 | mem: Adding verbose debug output in the memory system | Uri Wiener |
| 2013-03-27 | mem: Fix cache latency bug | Mitch Hayenga |
| 2013-02-19 | mem: Fix sender state bug and delay popping | Andreas Hansson |
| 2013-02-19 | scons: Fix up numerous warnings about name shadowing | Andreas Hansson |
| 2013-02-19 | mem: Enforce strict use of busFirst- and busLastWordTime | Andreas Hansson |
| 2013-02-19 | mem: Change accessor function names to match the port interface | Andreas Hansson |
| 2013-02-19 | mem: Make packet bus-related time accounting relative | Andreas Hansson |
| 2013-02-19 | sim: Make clock private and access using clockPeriod() | Andreas Hansson |
| 2013-02-19 | mem: Add predecessor to SenderState base class | Andreas Hansson |
| 2013-02-15 | mem: Tighten up cache constness and scoping | Andreas Hansson |
| 2013-02-15 | sim: Add a system-global option to bypass caches | Andreas Sandberg |
| 2013-01-07 | mem: Fix guest corruption when caches handle uncacheable accesses | Andreas Sandberg |
| 2013-01-07 | cache: add note about where conflicts are handled | Ali Saidi |
| 2012-11-02 | mem: Add support for writing back and flushing caches | Andreas Sandberg |
| 2012-10-15 | Mem: Use cycles to express cache-related latencies | Andreas Hansson |
| 2012-09-25 | Cache: add a response latency to the caches | Mrinmoy Ghosh |
| 2012-09-19 | AddrRange: Transition from Range<T> to AddrRange | Andreas Hansson |
| 2012-09-11 | Cache: Split invalidateBlk up to seperate block vs. tags | Lena Olson |
| 2012-08-22 | Packet: Remove NACKs from packet and its use in endpoints | Andreas Hansson |
| 2012-08-22 | Port: Extend the QueuedPort interface and use where appropriate | Andreas Hansson |
| 2012-07-27 | cache: don't allow dirty data in the i-cache | Anthony Gutierrez |
| 2012-07-09 | Port: Align port names in C++ and Python | Andreas Hansson |
| 2012-07-09 | Port: Make getAddrRanges const | Andreas Hansson |
| 2012-07-09 | Port: Add isSnooping to slave port (asking master port) | Andreas Hansson |
| 2012-06-29 | Mem: fix master id assertion in cache_impl.hh | Dam Sunwoo |
| 2012-06-29 | Cache: Only invalidate a line in the cache when an uncacheable write is seen. | Ali Saidi |
| 2012-06-07 | mem: Delay deleting of incoming packets by one call. | Ali Saidi |
| 2012-06-05 | sim: Remove FastAlloc | Ali Saidi |
| 2012-05-30 | Bus: Turn the PortId into a transport function parameter | Andreas Hansson |
| 2012-05-30 | Packet: Unify the use of PortID in packet and port | Andreas Hansson |
| 2012-05-10 | Cache: restructure code that actually isn't a loop | Ali Saidi |
| 2012-05-10 | Cache: Panic if you attempt to create a checkpoint with a cache in the system | Ali Saidi |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-14 | MEM: Remove the Broadcast destination from the packet | Andreas Hansson |
| 2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-03-22 | MEM: Split SimpleTimingPort into PacketQueue and ports | Andreas Hansson |
| 2012-03-09 | cache: Allow main memory to be at disjoint address ranges. | Ali Saidi |
