gem5 - gem5

Age	Commit message (Expand)	Author
2013-01-07	cache: add note about where conflicts are handled	Ali Saidi
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-11	Cache: Split invalidateBlk up to seperate block vs. tags	Lena Olson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-22	Port: Extend the QueuedPort interface and use where appropriate	Andreas Hansson
2012-07-27	cache: don't allow dirty data in the i-cache	Anthony Gutierrez
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-07-09	Port: Add isSnooping to slave port (asking master port)	Andreas Hansson
2012-06-29	Mem: fix master id assertion in cache_impl.hh	Dam Sunwoo
2012-06-29	Cache: Only invalidate a line in the cache when an uncacheable write is seen.	Ali Saidi
2012-06-07	mem: Delay deleting of incoming packets by one call.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-05-30	Bus: Turn the PortId into a transport function parameter	Andreas Hansson
2012-05-30	Packet: Unify the use of PortID in packet and port	Andreas Hansson
2012-05-10	Cache: restructure code that actually isn't a loop	Ali Saidi
2012-05-10	Cache: Panic if you attempt to create a checkpoint with a cache in the system	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-01	Cache: Fix an issue with LRU when bonus block is used to complete transaction.	Ali Saidi
2012-02-24	MEM: Simplify cache ports preparing for master/slave split	Andreas Hansson
2012-02-12	mem: fix cache stats to use request ids correctly	Dam Sunwoo
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-01-31	MEM: Remove the otherPort from the cache ports	Andreas Hansson
2012-01-17	MEM: Remove the functional ports from the memory system	William Wang
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Remove Port removeConn and MemObject deletePortRefs	Andreas Hansson
2012-01-17	MEM: Simplify ports by removing EventManager	Andreas Hansson
2012-01-17	MEM: Differentiate functional cache accesses from CPU and memory	Andreas Hansson
2011-09-13	Prefetch: Don't prefetch if address is in the write queue.	Ali Saidi
2011-08-19	Mem: Put prefetcher notify call before packet is deleted.	Ali Saidi
2011-08-19	Prefetcher: Fix some memory leaks with the prefetcher.	Ali Saidi
2011-07-15	Mem: Fix issue with prefetches originating at non-L1 caches getting stale data	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-10-18	cache: minor SC assertion fix	Steve Reinhardt
2010-10-13	Mem: Change the CLREX flag to CLEAR_LL.	Gabe Black
2010-09-21	cache: improve coherence handling of writebacks	Steve Reinhardt
2010-09-09	cache: fail SC when invalidated while waiting for bus	Steve Reinhardt
2010-09-09	mem: fix functional accesses to deal with coherence change	Steve Reinhardt