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path: root/src/mem/cache/cache_impl.hh
AgeCommit message (Expand)Author
2013-01-07cache: add note about where conflicts are handledAli Saidi
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-11Cache: Split invalidateBlk up to seperate block vs. tagsLena Olson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
2012-07-27cache: don't allow dirty data in the i-cacheAnthony Gutierrez
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-06-29Mem: fix master id assertion in cache_impl.hhDam Sunwoo
2012-06-29Cache: Only invalidate a line in the cache when an uncacheable write is seen.Ali Saidi
2012-06-07mem: Delay deleting of incoming packets by one call.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-05-30Bus: Turn the PortId into a transport function parameterAndreas Hansson
2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
2012-05-10Cache: restructure code that actually isn't a loopAli Saidi
2012-05-10Cache: Panic if you attempt to create a checkpoint with a cache in the systemAli Saidi
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-01Cache: Fix an issue with LRU when bonus block is used to complete transaction.Ali Saidi
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-01-31MEM: Remove the otherPort from the cache portsAndreas Hansson
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
2012-01-17MEM: Differentiate functional cache accesses from CPU and memoryAndreas Hansson
2011-09-13Prefetch: Don't prefetch if address is in the write queue.Ali Saidi
2011-08-19Mem: Put prefetcher notify call before packet is deleted.Ali Saidi
2011-08-19Prefetcher: Fix some memory leaks with the prefetcher.Ali Saidi
2011-07-15Mem: Fix issue with prefetches originating at non-L1 caches getting stale dataAli Saidi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-10-18cache: minor SC assertion fixSteve Reinhardt
2010-10-13Mem: Change the CLREX flag to CLEAR_LL.Gabe Black
2010-09-21cache: improve coherence handling of writebacksSteve Reinhardt
2010-09-09cache: fail SC when invalidated while waiting for busSteve Reinhardt
2010-09-09mem: fix functional accesses to deal with coherence changeSteve Reinhardt