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cache_impl.hh
Age
Commit message (
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Author
2010-08-23
MEM: Make CLREX a first class request operation and clear locks in caches whe...
Gene Wu
2010-08-23
ARM: Make sure that software prefetch instructions can't change the state of ...
Gene Wu
2010-07-22
Port: Only indicate that a SimpleTimingPort is drained if its send event is
Timothy M. Jones
2010-07-08
cache: fix bug in SC upgrade handling
Steve Reinhardt
2010-06-22
cache: fix longstanding prefetcher bug
Steve Reinhardt
2010-06-16
cache: fail store conditionals when upgrade loses race
Steve Reinhardt
2010-06-16
cache: fix dirty bit setting
Steve Reinhardt
2010-02-23
cache: Make caches sharing aware and add occupancy stats.
Lisa Hsu
2010-01-12
cache: make tags->insertBlock() and tags->accessBlock() context aware so that...
Lisa Hsu
2009-09-26
Minor cleanup: Use the blockAlign() method where it applies in the cache.
Steve Reinhardt
2009-09-26
Force prefetches to check cache and MSHRs immediately prior to issue.
Steve Reinhardt
2009-08-01
Fix setting of INST_FETCH flag for O3 CPU.
Steve Reinhardt
2009-05-17
includes: sort includes again
Nathan Binkert
2009-05-17
types: Move stuff for global types into src/base/types.hh
Nathan Binkert
2008-07-16
mem: use single BadAddr responder per system.
Steve Reinhardt
2009-04-19
Mem: Change isLlsc to isLLSC.
Gabe Black
2009-04-19
Memory: Rename LOCKED for load locked store conditional to LLSC.
Gabe Black
2009-03-11
cache: set dirty bit on swaps (oops!)
Steve Reinhardt
2009-02-16
Fixes to get prefetching working again.
Steve Reinhardt
2008-11-10
Cache: Refactor packet forwarding a bit.
Steve Reinhardt
2008-11-04
decouple eviction from insertion in the cache.
Lisa Hsu
2008-11-04
Change the findBlock(addr, lat) to accessBlock, which I think has better conn...
Lisa Hsu
2008-11-04
get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
Lisa Hsu
2008-10-09
eventq: convert all usage of events to use the new API.
Nathan Binkert
2008-06-28
Backed out changeset 94a7bb476fca: caused memory leak.
Steve Reinhardt
2008-06-21
Generate more useful error messages for unconnected ports.
Steve Reinhardt
2008-06-13
Get rid of bogus cache assertion.
Steve Reinhardt
2008-03-25
Fix handling of writeback-induced writebacks in atomic mode.
Steve Reinhardt
2008-03-24
Don't FastAlloc MSHRs since we don't allocate them on the fly.
Steve Reinhardt
2008-03-22
Fix cache problem with writes to tempBlock
Steve Reinhardt
2008-03-17
Fix a few Packet memory leaks.
Steve Reinhardt
2008-03-15
Fix subtle cache bug where read could return stale data
Steve Reinhardt
2008-02-26
Revamp cache timing access mshr check to make stats sane again.
Steve Reinhardt
2008-02-26
Cache: better comments particularly regarding writeback situation.
Steve Reinhardt
2008-02-16
Make L2+ caches allocate new block for writeback misses
Steve Reinhardt
2008-02-10
Fix #include lines for renamed cache files.
Steve Reinhardt
2008-01-06
Temporary fix for ll/sc bug see flyspray task for more info:
Geoffrey Blake
2008-01-02
Add ReadRespWithInvalidate to handle multi-level coherence situation
Steve Reinhardt
2008-01-02
Don't DPRINTF in the middle of a PrintReq.
Steve Reinhardt
2008-01-02
Add functional PrintReq command for memory-system debugging.
Steve Reinhardt
2008-01-02
Fix formatting and comments in cache_impl.hh
Steve Reinhardt
2007-11-16
Tweak check for writable block fill.
Steve Reinhardt
2007-09-16
mem: clean up bus/cache DPRINTFs a bit
Steve Reinhardt
2007-08-30
params: Deprecate old-style constructors; update most SimObject constructors.
Miles Kaufmann
2007-08-26
Merge with head
Gabe Black
2007-08-12
MemorySystem: Fix the use of ?: to produce correct results.
Ali Saidi
2007-08-10
DMA: Add IOCache and fix bus bridge to optionally only send requests one
Ali Saidi
2007-07-29
memory system: fix functional access bug.
Steve Reinhardt
2007-07-27
cache/memtest: fixes for functional accesses.
Steve Reinhardt
2007-07-27
cache: Get rid of unused variable.
Steve Reinhardt
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